Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

CL-PD6833-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name
Description
MFG CO.
CL-PD6833-VC-A
Cirrus-Logic
Cirrus Logic Cirrus-Logic
'CL-PD6833-VC-A' PDF : 216 Pages View PDF
CL-PD6833
PCI-to-CardBus Host Adapter
11.7.5 GPIO Output Control
Register Name: GPIO Output Control
I/O Index: 2Fh Extended Index: 18h
Memory Offset: 918h
Register Per: chip
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W:0
Reserved
R/W:0
R/W:0
R/W:0
GPIO4 Output GPIO3 Output GPIO2 Output GPIO1 Output
Control
Control
Control
Control
R/W:0
R/W:0
R/W:0
R/W:0
Bits 3:0 — GPIO[4:1] Output Control
When these bits are ‘0’, the corresponding GPIO pin is put into the high-impedance state. Setting
these bits causes the corresponding GPIO Output Data bit to be driven onto the corresponding
GPIO pin. If the corresponding GPIO Input Control bit is low, the output drives both active high and
active low. If the corresponding GPIO Input Control bit is high, the output is open-drain and drives
low only.
Bits 7:4 — Reserved
11.7.6 GPIO Input Control
Register Name: GPIO Input Control
I/O Index: 2Fh Extended Index: 19h
Memory Offset: 919h
Register Per: chip
Register Compatibility Type: ext.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
GPIO4
GPIO3
GPIO2
GPIO1
GPIO4 Input GPIO3 Input GPIO2 Input GPIO1 Input
Pull-up Enable Pull-up Enable Pull-up Enable Pull-up Enable Control
Control
Control
Control
R/W:0
R/W:0
R/W:0
R/W:0
R/W:0
R/W:0
R/W:0
R/W:0
Bits 3:0 — GPIO[4:1] Input Control
When these bits are set to ‘0’, the corresponding inputs are disabled and read back ‘1’s. This is
used to prevent floating inputs from drawing excessive power. When these bits are set, the data
read from the GPIO Input Data register reflects the value on the corresponding pin. If enabled, a
floating input can cause excessive power consumption, and can cause the other inputs to operate
incorrectly. If the corresponding GPIO Output Control bit is set, the pin is an output, regardless of
the state of the GPIO Input Control bit.
Bits 7:4 — GPIO[4:1] Pull-up Enable
0
GPIO pin tristate or open-collector per register 918h and 919h.
1
GPIO pin pull-up resistor to ‘+5V’ pin’s supply, except when outputting ‘0’.
June 1998
ADVANCE DATA BOOK v0.3
EXTENSION REGISTERS
147
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]