CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
1.5 Microcontroller Core
The CMX850 microcontroller core is software and cycle-timing compatible with the industry standard 80C51
and includes standard hardware such as a 256-byte local RAM, timer/counters, serial interface and interrupt
controller. The microcontroller architecture is further enhanced by the addition of extra core functionality
along with a comprehensive set of on-chip “peripheral” hardware. These are controlled by new registers
mapped into the 8051’s Special Function Register space. These additional features include:
• Dual data pointers
• 8kbyte on-chip XRAM
• General-purpose ports (up to 35 pins) with explicit direction and open-drain control, and optional
pull-up resistors
• External 64kbyte program address space, extendable using bank switching
• Four independently selectable XRAM source/destination areas, including on-chip XRAM and three
off-chip areas accessible through separate chip select pins
• Optional “MOVX” wait state for slow external peripherals
• 8 extra interrupts
• Advanced oscillator and power saving controls
• C-BUS controller connected to on-chip DSP modem
• Keyboard encoder (up to 128 keys)
• Dual channel 10-bit ADC with threshold comparators and internal bandgap reference
• Real time clock and alarm
• Watchdog timer
• Dual pulse-width modulators
• Debugger support through the use of a super priority interrupt pin
This datasheet contains a detailed description of the features unique to the CMX850 device. For a more
detailed description of the 8051 µC architecture, instruction set, timers, serial port, interrupts and CPU
timing, reference should be made to Programmers Guides, Hardware Descriptions and similar
documentation on the 8051 µC architecture, which is widely available. Please contact CML Technical
Support in case of difficulty.
© 2003 CML Microsystems Plc
17
D/850/6
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