CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
1.5.3.1 Port Data Registers (P0-P5)
The 8051 µC retains the standard port registers (P0, P1, P2, P3) as well as having two new ports, P4 and
P5. Writing to these port SFRs loads the associated output data register, which gets driven onto those
device pins that are configured as outputs. Reading from a port SFR will either read the contents of the port
output data register, or read directly from the port pins, depending on which instruction is used. The
instructions that read the data register rather than the pins are those that perform a read-modify-write
operation on a port or a port bit (this is explained in more detail in any standard 8051 µC documentation).
P0: SFR Address $80
P1: SFR Address $90
P2: SFR Address $A0
P3: SFR Address $B0
P4: SFR Address $C0
P5: SFR Address $D8
All bits set to 1 on reset. These registers are bit addressable.
Bit:
7
6
5
4
3
2
1
0
Bits 7-0 of the port data registers
1.5.3.2 Port Direction Registers (P0DIR-P5DIR)
Ports 0, 1, 3, 4 and 5 each have a direction control register that allows individual port pins to be configured
either as an input or an output. The bits should be cleared to a 0 for an input, or set to 1 for an output.
P0DIR: SFR Address $94
P1DIR: SFR Address $91
P3DIR: SFR Address $B1
P4DIR: SFR Address $C1
P5DIR: SFR Address $D9
All bits cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
Bits 7-0 of the direction control register
1.5.3.3 Port Open-Drain Registers (P1OD-P5OD)
Ports 1, 3, 4 and 5 each have an open-drain control register which allows individual port outputs to be
configured either with a pull-up/pull-down driver or with an open-drain driver. The bits should be cleared to a
0 for an active pull-up/pull-down driver, or set to 1 for an open-drain driver. Note that if a pin is configured
as an input by the port direction control register, then the pin driver will go into a high impedance state
irrespective of the contents of the associated open-drain control register bit.
P1OD: SFR Address $92
P3OD: SFR Address $B2
P4OD: SFR Address $C2
P5OD: SFR Address $DA
All bits cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
Bits 7-0 of the open-drain control register
© 2003 CML Microsystems Plc
21
D/850/6
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