CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
1.5.5 Interrupts
The 8051 µC interrupt logic has been extended, so that the original five interrupt sources (Int0, Timer0, Int1,
Timer1, Serial) have been supplemented by eight new interrupt sources (Int2, Int3, Int4, Int5, Int6, Int7, Int8
and Int9). With the exception of Int9, these new interrupts are connected to the 8051 µC’s on-chip peripheral
hardware logic as shown in Table 3, so that the hardware can be interrupt driven. Int9 is a super priority
interrupt, which can interrupt both low and high priority interrupts, and is available on a device pin when the
CMX850 is configured with a multiplexed memory address/data bus. This pin may be driven by an external
ROM emulator to assist with program debugging.
Interrupt signal
Hardware source
Int2
(Int0)
Int3
(Timer0)
Int4
(Int1)
Int5
(Timer1)
Int6
(Serial)
Int7
Int8
Int9
CAS Detect
Interrupt 0 input pin (P3.2)
DSP Modem
8051 timer 0
Keyboard encoder
Interrupt 1 input pin (P3.3)
A/D converter
8051 timer 1
RTC time interrupt
RI or TI from 8051 serial port
RTC alarm interrupt
Watchdog timeout
Interrupt 9 input pin (D6)*
Vector
address
$33
$03
$3B
$0B
$43
$13
$4B
$1B
$53
$23
$5B
$63
$6B
Priority within
level
1 (Highest)
2
3
4
5
6
7
8
9
10
11
12 (Lowest)
N/A (super priority)
* Note: D6 is only available as an interrupt with a multiplexed memory interface (pin MUXAD = 1)
Table 3 Interrupt structure
The “priority within level” structure is only used to resolve simultaneous interrupt requests of the same
priority level. A low priority interrupt which is active cannot be interrupted by another low priority interrupt,
but can be interrupted by a high priority interrupt or a super priority interrupt (Int9). A high priority interrupt
which is active can only be interrupted by Int9.
The new interrupts operate in a similar way to the existing Int0 and Int1 interrupts. Two new SFRs (IE_1 and
IP_1) allow the interrupts to be individually enabled and have their priority set, and new SFRs ICON1A and
ICON1B allow the interrupts to be configured as falling-edge or low-level triggered. In particular, the existing
global interrupt enable bit (IE register bit 7) can be used to disable all of the new interrupts with the
exception of Int9. It is recommended that the interrupts connected to the on-chip peripheral hardware (i.e.
Int2 … Int8) be configured as low-level triggered, with the application software explicitly clearing the
interrupts by using the relevant mechanism built into each hardware block. Note that pin D6 does not have
an on-chip pull-up resistor, so if this pin is used as a super priority interrupt (Int9) and is driven from a
device with an open-drain output driver, an external pull-up resistor will need to be added.
Further information about the Serial Port transmit/receive interrupt flags and the Int1-0 interrupt type control
and edge flags can be found in the description of the SCON and TCON registers.
© 2003 CML Microsystems Plc
25
D/850/6
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