Communications Controller
CMX850
1.5.5.1 Interrupt Enable Registers (IE, IE_1)
IE: SFR Address $A8
Bits b7 and b4-0 cleared to 0 on reset. Bits b6-5 unused. This register is bit addressable.
Bit:
7
6
5
4
3
2
1
0
Global
Interrupt
enable
(EA)
Unused
(set to 0)
Unused
(set to 0)
Serial port
interrupt
enable
(ES)
Timer 1
interrupt
enable
(ET1)
Int1 (P3.3)
interrupt
enable
(EX1)
Timer 0
interrupt
enable
(ET0)
Int0 (P3.2)
interrupt
enable
(EX0)
IE bits 4-0 can be used to individually enable each of the five standard 8051 interrupts: setting a bit
to 1 enables the interrupt, clearing the bit to 0 disables the interrupt. Furthermore, all CMX850
interrupts with the exception of Int9 (i.e. Serial, Timer 1-0, Int 8-0) can be globally disabled by
writing 0 to register IE bit 7 (EA).
IE_1: SFR Address $A9
Bits b7-0 cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
Int9
(pin D6)
interrupt
enable
Int8
interrupt
enable
Watchdog
Int7
interrupt
enable
RTC alarm
Int6
interrupt
enable
RTC time
Int5
interrupt
enable
ADC
Int4
interrupt
enable
Keyboard
Int3
interrupt
enable
C-BUS
Int2
interrupt
enable
CAS Det.
IE_1 bits 7-0 can be used to individually enable each of the eight new interrupts on the CMX850:
setting a bit to 1 enables the interrupt, clearing the bit to 0 disables the interrupt.
1.5.5.2 Interrupt Priority Registers (IP, IP_1)
IP: SFR Address $B8
Bits b4-0 cleared to 0 on reset. Bits b7-5 unused. This register is bit addressable.
Bit:
7
6
5
4
3
2
1
0
Unused
(set to 0)
Unused
(set to 0)
Unused
(set to 0)
Serial port
interrupt
priority
(PS)
Timer 1
interrupt
priority
(PT1)
Int1
interrupt
priority
(PX1)
Timer 0
interrupt
priority
(PT0)
Int0
interrupt
priority
(PX0)
IP bits 4-0 can be used to set the priority level of the Serial Port, Timer1, Timer0, Int1 and Int0
interrupts: setting a bit to 1 configures the interrupt as high priority, clearing the bit to 0 configures
the interrupt as low priority.
© 2003 CML Microsystems Plc
26
D/850/6