CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
1.5.4 Memory Interface
In addition to 256 bytes of scratchpad RAM, the CMX850 has 8kbytes of on-chip extension RAM (XRAM)
and three separate 64k areas for off-chip memory and peripherals, accessible without glue logic via chip
select pins CSN1, CSN2 and CSN3. External memory size can easily be increased to several megabytes by
using a code-banking compiler along with a number of CMX850 port output pins as bank select bits.
The CSN1 pin is normally used during program instruction fetches, although there is an option to replace
the bottom 8kbytes of off-chip program ROM with the on-chip XRAM, allowing short sections of temporary
program code to be executed from the on-chip XRAM. This could be used, for instance, when the CMX850
is re-programming external FLASH memory.
MOVX read and write instructions can be independently directed to either the on-chip XRAM or any of the
three off-chip memory areas, including the program ROM area (this allows the CMX850 to re-program
external FLASH memory, if necessary). Combined with the dual data pointer architecture of the CMX850
microcontroller, this allows rapid block moves between any of the memory areas. The MOVX read and write
instructions can also be independently stretched to allow access to slow memory or peripherals, without any
external circuitry being required.
All off-chip accesses use the same 16-bit address bus and 8-bit data bus, along with output enable (OEN)
and write enable (WEN) control pins. The address and data pins can be configured to be non-multiplexed by
tying input pin MUXAD low (address output on pins A15-0, bi-directional data uses pins D7-0), or the data
can be multiplexed with the lower eight address pins (A7-0) by tying input pin MUXAD high.
If configured with a multiplexed address/data bus, an external address latch (‘373 or '573 type) is required.
Pin D7 becomes an address latch enable (ALE), and pins D6-0 are reassigned as an extra interrupt pin and
general-purpose port bits. During the time when ALE is high, the least significant byte (LSB) of the 16-bit
memory address is driven onto pins A7-0. When ALE goes low, the LSB of the memory address gets held in
the external address latch, and the A7-0 pins change to a bi-directional data bus.
In order to minimise power consumption and EMI, the CMX850 only performs program memory reads when
necessary, rather than doing continuous reads and discarding the unnecessary ones as on a standard 8051.
This typically reduces the number of program read operations by 30% - 40%. Furthermore, when using a
multiplexed address/data bus, unnecessary ALE pulses are inhibited.
The CMX850 data pins (D7-0 for non-multiplexed, or A7-0 for multiplexed) can be configured with weak
bus-holding devices to prevent voltage drift on the pins during long periods of inactivity (e.g. when in
idle/power down mode, or executing programs from entirely within on-chip XRAM). This can help reduce
unnecessary current consumption in devices connected to the data bus.
The memory interface is configured using the MEMCON SFR.
1.5.4.1 Memory Control Register (MEMCON)
MEMCON: SFR Address $FA
All bits cleared to 0 on reset.
Bit:
7
6
5
Enable Internal
bus-hold progam
MOVX
write
stretch
4
3
MOVX write
destination
2
MOVX
read
stretch
1
0
MOVX read source
© 2003 CML Microsystems Plc
23
D/850/6
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