CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
IP_1: SFR Address $B9
Bits b6-0 cleared to 0 on reset. Bit b7 unused.
Bit:
7
6
5
4
Unused
(set to 0)
Int8
interrupt
priority
Int7
interrupt
priority
Int6
interrupt
priority
Watchdog RTC alarm RTC time
3
Int5
interrupt
priority
ADC
2
Int4
interrupt
priority
Keyboard
1
Int3
interrupt
priority
C-BUS
0
Int2
interrupt
priority
CAS Det.
IP_1 bits 6-0 can be used to set the priority level of interrupts Int8-2: setting a bit to 1 configures the
interrupt as high priority, clearing the bit to 0 configures the interrupt as low priority. The Int9
interrupt is permanently configured with a super high priority, enabling it to interrupt any other
currently active low or high priority interrupt.
1.5.5.3 Interrupt Control Registers (ICON1A/B)
Each of the new interrupt inputs in the 8051 µC has two associated control/status bits, residing in registers
ICON1A and ICON1B. These operate in an identical way to the existing Int0 and Int1 control and status bits
in the TCON register.
Type control: these bits are set to 1 or cleared to 0 by software to configure the interrupts as falling-edge or
low-level triggered respectively. It is recommended that the type control bits for Int8-2 be cleared to 0, i.e.
configured as low-level triggered.
Edge flag: when the interrupt is configured as falling-edge triggered, these bits are set to 1 by hardware to
indicate that an edge has been detected, i.e. successive samples of the interrupt pin show a high in one
machine cycle and a low in the next cycle, and will be cleared automatically when the service routine is
called. When configured as low-level triggered interrupts, the edge flag will be updated once per cycle to
reflect the state of the associated interrupt signal; the flag gets set to 1 if the interrupt line is active (i.e. low),
and gets cleared to 0 if the interrupt line is inactive (high).
ICON1A: SFR Address $AA
All bits cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
Int5 edge Int5 type Int4 edge Int4 type Int3 edge Int3 type Int2 edge Int2 type
flag
control
flag
control
flag
control
flag
control
ICON1B: SFR Address $AB
All bits cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
Int9 edge Int9 type Int8 edge Int8 type Int7 edge Int7 type Int6 edge Int6 type
flag
control
flag
control
flag
control
flag
control
© 2003 CML Microsystems Plc
27
D/850/6
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