CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
MEMCON Register b7: Enable bus-hold
b7 = 1 Enable data pin bus-holding devices
b7= 0 Disable data pin bus-holding devices
MEMCON Register b6: Internal program
b6 = 1 On-chip XRAM mapped into bottom 8Kbytes of program memory
b6 = 0 Program memory is entirely off-chip
Allows temporary program code to be executed from on-chip XRAM. Note that any interrupt service
routine vectors being used (these begin at locations $03 to $6B) should be duplicated in XRAM
before setting this bit; alternatively the interrupts should be disabled. When MEMCON bit 6 is
altered, even though the instruction that modifies it executes in the normal amount of time, there is
an internal delay of 2 machine cycles before the switch between ROM and XRAM takes effect.
MEMCON bit 6 can be changed without any problems when program execution is taking place in
external ROM at an address of $2000 or above. Changing MEMCON bit 6 when program execution
is taking place in external ROM or internal XRAM at an address between $0000 and $1FFF requires
some care to prevent disruption of the desired program flow.
MEMCON Register b5: MOVX write stretch
b5 = 1 MOVX write operations are stretched by one machine cycle (12 xtal cycles)
b5 = 0 MOVX write operations are not stretched
MEMCON Register b4-3: MOVX write destination
b4 b3
0 0 MOVX write destination is on-chip XRAM
0 1 MOVX write destination is off-chip, using pin CSN1
1 0 MOVX write destination is off-chip, using pin CSN2
1 1 MOVX write destination is off-chip, using pin CSN3
MEMCON Register b2: MOVX read stretch
b2 = 1 MOVX read operations are stretched by one machine cycle (12 xtal cycles)
b2 = 0 MOVX read operations are not stretched
MEMCON Register b1-0: MOVX read source
b1 b0
0 0 MOVX read source is on-chip XRAM
0 1 MOVX read source is off-chip, using pin CSN1
1 0 MOVX read source is off-chip, using pin CSN2
1 1 MOVX read source is off-chip, using pin CSN3
© 2003 CML Microsystems Plc
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D/850/6
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