Qdatasheet_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

CMX850L8 View Datasheet(PDF) - CML Microsystems Plc

Part Name
Description
MFG CO.
CMX850L8
CML
CML Microsystems Plc CML
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
OSCCON Register b3: System crystal frequency select
This bit should be set according to the system Xtal frequency being used. It is used to select the
division ratio when the 32.768kHz reference is being derived from the main system clock (see
description of OSCCON bit 0), and is also used to configure the DSP modem’s clock dividers. This
bit must be set to the correct state before the modem is used.
b3 = 1 System Xtal frequency is 11.0592MHz
b3 = 0 System Xtal frequency is 12.288MHz
OSCCON Register b2: 32.768kHz clock output enable
This bit can be used to drive the 32.768kHz reference signal onto the X32KN pin for use by external
circuitry. This can only be done if the 32.768kHz signal is derived from the main system clock; the
function is disabled if using an external 32.768kHz Xtal reference (see description of OSCCON bit
0).
b2 = 1 Drive internal 32.768kHz reference onto X32KN pin (only if OSCCON bit 0 =
0)
b2 = 0 Do not drive internal 32.768kHz reference onto X32KN pin
OSCCON Register b1: 32.768kHz clock power down
Controls whether the 32.768kHz clock is power saved when the 8051 µC is in power down mode
(power down mode is enabled by writing 1 to PCON bit 1). This depends on whether any of the
peripheral blocks that use the 32.768kHz clock (i.e. RTC, WDT, Keyboard encoder) need to remain
active during 8051 power down.
b1 = 1 32.768kHz clock remains active during 8051 power down
b1 = 0 32.768kHz clock power saved during 8051 power down
OSCCON Register b0: 32.768kHz clock source select
Controls whether the 32.768kHz clock is derived from a divided down main system clock (thus
saving the expense of an external 32.768kHz Xtal), or uses the external Xtal (which allows the
32.768kHz clock to remain active while the system clock is powered down). If dividing down from
the main system clock, the division ratio depends on whether an 11.0592MHz or 12.288MHz Xtal is
used (see OSCCON bit 3), or whether the RC oscillator is selected. The accuracy of the 32.768kHz
clock will only be as good as that of the selected reference source, which in the case of the RC
oscillator is not good enough to maintain the correct time and date in the RTC.
b0 = 1
b0 = 0
32.768kHz clock source is external Xtal
32.768kHz clock derived from main system clock:
OSCCON b4 - 3 System clock division ratio
0
X
1
0
168¾
375
(Due to odd division ratios, derived clock edge
will jitter slightly but frequency will be accurate)
1
1
337½
© 2003 CML Microsystems Plc
31
D/850/6
Share Link: GO URL

All Rights Reserved © qdatasheet.com  [ Privacy Policy ] [ Contact Us ]