CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
PDXMASK: SFR Address $9F
All bits cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
Int8 exit
mask
Int7 exit
mask
Int6 exit
mask
Int5 exit
mask
Int4 exit
mask
Int3 exit
mask
Int2 exit
mask
Int0 exit
mask
CMX850
1.5.6.5 Power Control Register (PCON)
PCON: SFR Address $87
Bits b7 and b3-0 cleared to 0 on reset. Bits b6-4 unused.
Bit:
7
6
5
4
3
2
1
0
Double
baud rate
(SMOD)
Unused
(set to 0)
Unused
(set to 0)
Unused
(set to 0)
General
purpose
flag
(GF1)
General
purpose
flag
(GF0)
Power
Down bit
(PD)
Idle Mode
bit
(IDL)
PCON Register b7: Double baud rate (SMOD)
If Timer 1 is used to generate the serial port baud rate and SMOD = 1, the baud rate is doubled
when the serial port is used in modes 1, 2 or 3.
PCON Register b6-4: Unused
PCON Register b3-2: General purpose flags (GF1, GF0)
PCON Register b1: Power Down bit (PD)
Setting this bit activates Power Down operation in the 8051 µC (all activity within the 8051 CPU
core and interrupt/serial port/timer logic is halted). It is possible to exit Power Down (i.e. clear
PCON bit 1) by applying a hardware reset to the CMX850, or by activating an interrupt which has its
associated mask bit in the PDXMASK register set (whether the interrupt is enabled or not).
PCON Register b0: Idle Mode bit (IDL)
Setting this bit activates Idle Mode operation in the 8051 µC (activity within the 8051 CPU core is
halted, but the interrupt/serial port/timer logic remains active). It is possible to exit Idle Mode (i.e.
clear PCON bit 0) by applying a hardware reset to the CMX850, or by activating an enabled
interrupt.
If Power Down and Idle Mode are activated simultaneously, Power Down takes precedence.
1.5.7 Pulse Width Modulators
The CMX850 has two independent 8-bit Pulse Width Modulator (PWM) circuits, each with its own PWM
data register (SFRs PWM1 and PWM2) and enable bit in the PWMCON SFR. When enabled, the PWM
output is automatically driven onto the relevant device pin (the PWM 1 output is driven onto pin P3.6, the
PWM 2 output is driven onto pin P3.7). This is done without altering the 8051’s port control SFRs.
Disabling a PWM causes its output pin to immediately revert to a general-purpose port function.
The output of each PWM block is a fixed frequency square wave with a duty cycle controlled by the
contents of the PWM1 or PWM2 SFR. The square wave frequency is 1/255 of the main system clock, i.e.
approximately 43.4kHz if using an 11.0592MHz crystal, 48.2kHz if using a 12.288 MHz crystal, or 21.6kHz
(nominal) if using the on-chip RC oscillator. The PWM output duty cycle is equal to PWM1 (or PWM2) *
(100/255)%: a value of $00 will cause a permanently low output, while a value of $FF will cause a
permanently high output, and a value of $13 (for example) will cause a waveform with a duty cycle of
© 2003 CML Microsystems Plc
34
D/850/6
Share Link: 
