CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
ADCCON2: SFR Address $E3
All bits cleared to 0 on reset.
Bit:
7
6
5
4
Output
data
left/right
justify
Continuous convert sample rate
3
Power-
save
track/hold
A
2
Power-
save
track/hold
B
1
Auto
power-
save
0
Input
select
ADCCON2 Register b7: Output data left/right justify
The output from the ADC is 10-bit, requiring two SFRs (ADCBUFL and ADCBUFH) to hold the data.
The SFRs therefore contain 6 spare bits, which are set to 0. ADCCON2 bit 7 determines whether
the 10-bit ADC conversion result is left- or right-justified within the ADCBUFL and ADCBUFH
registers. If the ADC is required for 8-bit conversions only, set this bit to 0 (left-justified), and then
only ADCBUFH needs to be read for the valid eight bit data, which is the most significant eight bits
of the conversion.
b7 = 1 Right-justify ADC data:
ADCBUFH
ADCBUFL
7 654321076543210
(set to 0)
ADC data bits 9-0
b7 = 0 Left-justify ADC data:
ADCBUFH
ADCBUFL
7 654321076543210
ADC data bits 9-0
(set to 0)
ADCCON2 Register b6-4: Continuous convert sample rate
These three bits select the rate at which conversions are done when continuous convert is enabled.
b6 b5 b4
0 0 1 Conversion rate = System clock frequency ÷ 8832
0 1 1 Conversion rate = System clock frequency ÷ 4416
1 0 1 Conversion rate = System clock frequency ÷ 2208
1 1 1 Conversion rate = System clock frequency ÷ 1104
X X 0 Conversion rate = System clock frequency ÷ 552
ADCCON2 Register b3: Power-save track/hold A
This bit is used to explicitly enable the track/hold A circuit, or power save and bypass it if the
track/hold function is not required or VINA is not being used. Track/hold A can also be power saved
between manual conversions to minimise power consumption, in which case it should be enabled at
least 25µs before a conversion is done on pin VINA. Power saving track/hold A using ADCCON2 bit
3 overrides the auto power save feature in continuous convert mode (see ADCCON2 bit 1). Hold
mode is selected automatically at the start of a conversion. The track/hold circuit returns to Track
mode when the conversion is complete.
b3 = 1 Enable track/hold A
b3 = 0 Power save and bypass track/hold A
© 2003 CML Microsystems Plc
39
D/850/6
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