CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
ADCCON1 Register b3: Inverted threshold mode
This bit selects the conditions for setting the threshold high/low interrupt status bits at the end of an
ADC conversion. It is possible to configure the comparators to indicate either when the ADC output
value goes outside the range defined by ADCTHRL/ADCTHRH, or when the ADC output value
enters that range (the most significant 8 bits of the ADC value are used in the comparison).
b3 = 1
b3 = 0
Threshold high and low interrupt status both set to 1 if ADC value
≤ ADCTHRH and ≥ ADCTHRL
Threshold high interrupt status set to 1 if ADC value > ADCTHRH
Threshold low interrupt status set to 1 if ADC value < ADCTHRL
If ADCCON1 bit 3 = 1, then both threshold status bits (ADCCON1 bit 6 and bit 4) get set
simultaneously, and must both be cleared to remove the interrupt.
It is possible to prevent the threshold high/low interrupt status bits from being set to 1 by setting
ADCCON bit 3 to 0, ADCTHRH to $FF, and ADCTHRL to $00. If, however, it is desired to always
generate an interrupt after a conversion (e.g. when in continuous convert mode), this can be done
by setting ADCCON bit 3 to 0, and setting ADCTHRH lower than ADCTHRL.
ADCCON1 Register b2: VREF control
This bit is used to select the source of the ADC reference voltage; the selected source is also driven
onto the VREF pin. If the internal track/hold circuitry is used in conjunction with AVDD as a
reference voltage, it may not be possible to obtain correct digital representations for input voltages
that are very close to AVDD itself.
b2 = 1 Use the on-chip 2.5V reference for the ADC
b2 = 0 Use AVDD as the ADC voltage reference, and power save the on-chip
2.5V reference generator
ADCCON1 Register b1: Continuous convert enable
This bit is used to enable continuous convert operation, when the ADC will automatically perform
conversions at a rate selected in the ADCCON2 register. This may be used in conjunction with the
threshold high/low comparators to perform signal monitoring without loading the 8051 µC. If
required, however, continuous convert can be used without the threshold comparator interrupt being
enabled. In this case, the Status bit (ADCCON1 bit 0) will have to be polled to determine when each
conversion ends. The data in the ADCBUFL and ADCBUFH registers can then be retrieved, before
the next conversion begins.
b1 = 1 Continuous convert enabled
b1 = 0 Continuous convert disabled
ADCCON1 Register b0: Manual start and status
This bit is written with a 1 to start an ADC conversion (writing a 0 has no effect). It may then be read
to determine when a conversion has completed, which will be within 156 cycles of the main system
clock (equivalent to thirteen 8051 machine cycles or about 14.1µs if using an 11.0592MHz crystal):
the status bit will read as a 1 while the conversion is taking place, and read as a 0 upon completion.
During this time, the ADCBUFL and ADCBUFH registers will contain invalid data.
The status bit can also be monitored in continuous convert mode; it is set to 1 when a conversion is
started, and cleared to 0 when it ends.
It is recommended that ADCCON1 bit 0 is not written with a 1 while continuous convert is enabled,
since the timing of the conversions and power save operations may be affected. It may, however,
be read from at any time to determine status.
© 2003 CML Microsystems Plc
38
D/850/6
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