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CMX850L8 View Datasheet(PDF) - CML Microsystems Plc

Part Name
Description
MFG CO.
CMX850L8
CML
CML Microsystems Plc CML
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
1.5.8 Analogue to Digital Converter
CMX850
Figure 6 Analogue to Digital Converter Block Diagram
The Analogue to Digital Converter (ADC) is a 10-bit successive approximation type converter that produces
an unsigned digital representation of an input voltage, selected from one of two input pins, in the range of
AVSS to VREF. The ADC output data is stored in two SFRs, ADCBUFL and ADCBUFH. The ADC can be
used to do one-shot conversions on command, or it can be used in a continuous convert mode with a
selectable sample rate of up to approximately 20kHz. A digital comparator can also be enabled which will
generate an interrupt request to the 8051 µC if the conversion value enters or leaves certain threshold
levels, as set in the SFRs ADCTHRL and ADCTHRH. This can be used with continuous convert mode to
automatically monitor a signal level, with no intervention by the 8051 µC being required.
Other features of the ADC include left- or right-hand justified conversion data, power saving features,
optional on-chip track/hold circuits, and a choice between a bandgap-derived voltage reference (VREF =
2.5V) or a supply reference (VREF = AVDD). The selected VREF voltage is driven off chip for user reference
through the VREF pin.
Note that VINA and VINB are sensitive analogue inputs, and should be carefully decoupled to AVSS to
reduce noise and instability in readings.
1.5.8.1 ADC Control Registers (ADCCON1/2)
The ADC has two control registers in the SFR space, ADCCON1 and ADCCON2.
When low power consumption is important and the ADC is not being used, the internal bandgap reference
must be disabled by setting b2 of ADCCON1 to 0 and the track/hold circuits should both be disabled by
setting b3 and b2 of ADCCON2 to 0. The 10-bit ADC converter circuit consumes no power between
conversions.
© 2003 CML Microsystems Plc
36
D/850/6
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