CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
SPDCON Register b7-4: 8051 µC clock speed select
b2 b1 b0
0 0 0 8051 speed reduction disabled
0 0 1 8051 clock speed = divide by 4
0 1 0 8051 clock speed = divide by 16
0 1 1 8051 clock speed = divide by 64
1 0 0 8051 clock speed = divide by 256
1 0 1 8051 clock speed = divide by 1024
1 1 0 Reserved (do not use)
1 1 1 Reserved (do not use)
CMX850
1.5.6.3 Speed Control Exit Register (SPXMASK)
This register can be configured to allow the 8051 µC to be brought immediately out of speed control mode
when any interrupt input line to the µC (chosen from Int8-2 and Int0) goes active, i.e. low. To enable an
interrupt to bring the 8051 µC out of speed control mode, its associated mask bit in the SPXMASK register
must be set to a 1, otherwise it should be cleared to 0. Note that the µC can be brought out of speed control
mode by an interrupt that is not enabled in the IE or IE_1 SFRs. This allows the speed control exit feature to
be used even in systems that poll the peripheral hardware rather than have it interrupt driven.
When an interrupt goes active whose mask bit is set to 1, the SPDCON register bits are all immediately
cleared to 0.
SPXMASK: SFR Address $9E
All bits cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
Int8 exit
mask
Int7 exit
mask
Int6 exit
mask
Int5 exit
mask
Int4 exit
mask
Int3 exit
mask
Int2 exit
mask
Int0 exit
mask
1.5.6.4 Power Down Exit Register (PDXMASK)
This register can be configured to allow the 8051 µC to be brought immediately out of power down mode
when any interrupt input line to the µC (chosen from Int8-2 and Int0) goes active, i.e. low. To enable an
interrupt to bring the 8051 µC out of power down mode, its associated mask bit in the PDXMASK register
must be set to a 1, otherwise it should be cleared to 0. Note that the µC can be brought out of power down
mode by an interrupt that is not enabled in the IE or IE_1 SFRs. This allows the power down exit feature to
be used even in systems that poll the peripheral hardware rather than have it interrupt driven.
When the 8051 µC is brought out of power down mode, register PCON bit 1 immediately gets cleared to 0
and the µC will then respond to any active, enabled interrupts. If no enabled interrupt is active, the µC will
continue program execution from the instruction following the one that put it into power down mode.
Note that if the CMX850 system clock source is configured as an external Xtal that gets disabled in power
down mode (see OSCCON register), it will take a number of milliseconds for the Xtal to start up again and
stabilise before the system begins clocking. If a more rapid response during a power down exit is required,
either the Xtal should remain running during power down or the system clock source should be configured to
be the RC oscillator before power down mode is entered.
© 2003 CML Microsystems Plc
33
D/850/6
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