CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
ADCCON2 Register b2: Power-save track/hold B
This bit is used to explicitly enable the track/hold B circuit, or power save and bypass it if the
track/hold function is not required or VINB is not being used. Track/hold B can also be power saved
between manual conversions to minimise power consumption, in which case it should be enabled at
least 25µs before a conversion is done on pin VINB. Power saving track/hold B using ADCCON2 bit
2 overrides the auto power save feature in continuous convert mode (see ADCCON2 bit 1). Hold
mode is selected automatically at the start of a conversion. The track/hold circuit returns to Track
mode when the conversion is complete.
b2 = 1 Enable track/hold B
b2 = 0 Power save and bypass track/hold B
ADCCON2 Register b1: Auto power save
This bit can be used to enable the auto power save feature when in continuous convert mode. This
causes both track/hold circuits to power down between conversions, and power up again in time for
each new conversion. To further save power when using continuous convert mode, the unused ADC
input should have its track/hold circuit disabled using ADCCON2 bit 2 or 3.
b1 = 1 Enable auto power save for continuous convert mode
b1 = 0 Disable auto power save for continuous convert mode
ADCCON2 Register b0: Input select
Selects which of the two ADC input channels is used for a conversion. This bit should not be
changed while a conversion is in progress, otherwise an invalid result will be obtained.
b0 = 1 Select pin VINB
b0 = 0 Select pin VINA
1.5.8.2 ADC Buffer Registers (ADCBUFL/H)
These two 8-bit buffer registers hold the 10-bit result from an ADC conversion. The data can be selected as
left- or right-hand justified by using ADCCON2 bit 7. These registers are not cleared on reset; the data
remains unknown until the first conversion is finished. The data is also invalid during each conversion.
ADCBUFL: SFR Address $E4
Bit:
7
6
5
4
3
2
1
0
Right
justified:
ADC data bits 7-0
Left
ADC data bits 1-0
0
0
0
0
0
0
justified:
ADCBUFH: SFR Address $E5
Bit:
7
6
5
4
3
2
1
0
Right
0
0
0
0
0
0
ADC data bits 9-8
justified:
Left
justified:
ADC data bits 9-2
© 2003 CML Microsystems Plc
40
D/850/6
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