CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
1.5.8.3 ADC Threshold Registers (ADCTHRL/H)
At the end of each ADC conversion, bits 9-2 of the ADC output data is compared against the contents of
both the ADCTHRL and ADCTHRH registers, which may set the threshold high/low interrupt status bits (see
the description of ADCCON1 bits 7-3).
ADCTHRL: SFR Address $E6
All bits cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
ADC low threshold value
ADCTHRH: SFR Address $E7
All bits cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
ADC high threshold value
1.5.9 C-BUS Controller
The C-BUS controller provides for the transfer of data and control between the 8051 µC and the DSP
modem’s internal registers over the C-BUS interface. The modem, described in full in section 1.6, has its
own registers that must be accessed using the C-BUS controller to allow the modem to operate as required.
Each transaction consists of a minimum of one byte sent from the µC, which may be followed by one or
more data byte(s) sent from the µC to be written into one of the modem’s Write Only Registers, or one or
more byte(s) of data read out from one of the modem’s Read Only Registers, as illustrated below.
The C-BUS controller is accessed by the 8051 µC through two SFRs, one for read/write data (CBUSBUF)
and the other for control (CBUSCON). A transaction is initiated when the 8051 µC sets the C-BUS select bit
in the CBUSCON register to 1. Command and data bytes may then be sent to the modem by writing to the
CBUSBUF register, which the C-BUS controller automatically shifts out to the modem. At the same time,
any reply data from the modem gets shifted back into the CBUSBUF register. To read a data byte from the
modem, therefore, the 8051 µC must perform a dummy byte write to the CBUSBUF register after the initial
write of a C-BUS Command to supply Reply Data. Reply data is stored in CBUSBUF every time a byte is
written, but is only valid when reading a register. Setting the C-BUS select bit in the CBUSCON register to 0
terminates a transaction. The time between one transaction being terminated and another being initiated
may be as small as a single 8051 machine cycle (i.e. 12 system clock cycles).
Data bytes may be written to the modem via the CBUSBUF register using back-to-back MOV instuctions.
However, when reading a data byte from the modem, at least one machine cycle (e.g. a NOP instruction)
must be inserted between the dummy CBUSBUF write and the CBUSBUF data read in order to give the
modem time to respond. Failure to do this will result in corruption of the data being read from the modem.
The modem also generates an active low interrupt output signal, IRQN, which is configured through a C-
BUS register within the modem. This IRQN signal is directly connected to the 8051 µC’s Int3 interrupt input.
This signal may also be polled by reading the CBUSCON register.
© 2003 CML Microsystems Plc
41
D/850/6
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