CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
1.5.11 Watchdog Timer
The Watchdog Timer (WDT) can be used to monitor the operation of the CMX850 system. This is achieved
by creating a regular WDT refresh within the software; if this refresh does not occur on time, the WDT will
assume that the system has hung and will cause a system reset, preceded by an optional interrupt request
to the 8051 µC.
The WDT is configured and controlled through two SFRs, WDTCON and WDTLD. The WDT can be
programmed to have a wide range of timeout values: it uses the 32.768kHz reference clock, prescaled by 1,
8, 64 or 256, to increment a 16-bit counter. A watchdog timeout occurs when this counter reaches $FFFF
and subsequently overflows. To prevent this happening, the application software should regularly refresh
the watchdog, causing the upper eight bits of the counter to be preloaded from the WDTLD register (the
lower eight bits of the counter are simultaneously reset to $00). By selecting the clock prescaler division
ratio and the WDTLD register value, a timeout value of between approximately 0.0078 seconds and 8.5
minutes can be programmed. The actual timeout period in seconds can be calculated as:
Timeout period = (256-WDTLD)*Prescale/128 (where Prescale = 1, 8, 64, or 256)
When a WDT timeout occurs, the CMX850 will be reset immediately unless the WDT has been configured
to first generate an interrupt. In that case, the active low Int8 input to the 8051 µC will be pulled down when
a WDT timeout occurs. If the WDT is then not refreshed by software, the CMX850 will be reset after a
further (Prescale *7.843) milliseconds, approximately. Note that if a WDT interrupt has occurred, a refresh
must be performed before changing any of the other configuration bits in the WDTCON register; this can be
done using an “ORL WDTCON,#02H” instruction. Failure to observe this precaution may cause a spurious
reset to be triggered.
The optional WDT interrupt gives the µC chance to deal with a watchdog timeout before the entire chip is
reset. The reset pulse generated by the WDT lasts for between three and four machine cycles.
Note that the WDT must be refreshed before being used for the first time after power up. This should be
done after the WDTLD register is written and the WDT is enabled, but before the WDT is started.
1.5.11.1
Watchdog Control Register (WDTCON)
WDTCON: SFR Address $F2
WDTCON bit 2 is cleared to 0 only when the device powers up, all other bits are cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
WDT
WDT prescale
Delayed
0
Timeout Refresh
Start
enable
reset
status
enable
WDTCON Register b7: WDT enable
The WDT enable bit is cleared to 0 whenever a reset occurs, whether from the RESETN pin or from
a WDT timeout. This bit must be set to 1 to enable the clock to the WDT circuitry, which then allows
the WDT to be started or refreshed.
b7 = 1 Enable WDT (requires 32.768kHz clock to be active)
b7 = 0 Disable and powersave the WDT
© 2003 CML Microsystems Plc
47
D/850/6
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