CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
RTC TIME1: SFR Address $FD
All bits unaffected by reset.
Bit:
7
6
5
4
3
2
1
0
Bits 15 - 8 of RTC TIME register
RTC TIME2: SFR Address $FE
All bits unaffected by reset.
Bit:
7
6
5
4
3
2
1
0
Bits 23 - 16 of RTC TIME register
RTC TIME3: SFR Address $FF
All bits unaffected by reset.
Bit:
7
6
5
4
3
2
1
0
Bits 31 - 24 of RTC TIME register
To use the clock features, bit 7 of RTCCON is set to 1 to enable the RTC. Then bit 3 of RTCCON is set to 1
to stop the clock counter. The four RTC TIME registers can now be written with the required value in
seconds, which can be used to represent a time and date with a suitable software algorithm. Once the
required value is stored, the clock can be started by clearing bit 3 of RTCCON. Once the time is set and the
clock enabled the value stored will be incremented once every second. The RTC operation will not be
suspended when a reset occurs as bits 7 and 3 of RTCCON are unaffected by a reset, so the time will
continue to be incremented once every second.
If the prescale reset (RTCCON bit 6) is set to 1 before the clock is started, then immediately set back to 0
after the clock is started, the internal fractions of a second will be reset to zero and the first increment of the
clock will occur after 1 second. However, if the time interrupt feature is already being used as described in
the RTC Control Register section above, and it is required to be accurate and continuous, then the
“fractions of a second” prescaler must remain running and the prescale reset must not be used. In this case
the first increment of the clock will be synchronised to the already continuously running fractions of a
second.
Note: to read the current 32-bit time value requires four reads, one from each of the four time registers.
Since each read takes a finite time there is a small probability that the time value may be incremented
between register reads, giving erroneous results. It is therefore recommended that the 32-bit time value be
read repeatedly until two successive 32-bit results match (this will normally happen after the first pair of 32-
bit reads). The value read will then be correct.
1.5.12.3
RTC Alarm Registers (ALM0-ALM3)
The RTC stores the alarm time in four SFRs: ALM0, ALM1, ALM2 and ALM3. Each register holds eight bits,
with ALM0 holding the least significant eight bits and ALM3 holding the most significant eight bits. Using the
alarm facility is simply a case of setting the required alarm time in ALM0…3. The RTC waits until the
current 32-bit time value is equal to or greater than the 32-bit alarm time, then on the next active edge of
the 32.768kHz clock will assert the Int7 interrupt line to the 8051 µC (i.e. drive it low). As it is recommended
that Int7 be configured as a level sensitive interrupt, it is the responsibility of the interrupt service routine to
clear the alarm interrupt request either by clearing IE_1 bit 5 or by writing a new 32-bit alarm value to the
ALM0…3 SFRs (writing to any of the ALM0…3 registers negates the Int7 signal). If this is not done, the
alarm interrupt will re-trigger upon exit of the service routine.
Note that a spurious interrupt request may be generated as the ALM0…3 registers are being updated by
software, since four write operations are needed. It is therefore recommended that the alarm interrupt
enable bit (IE_1 bit 5) be cleared whenever the ALM0…3 registers are being modified.
© 2003 CML Microsystems Plc
51
D/850/6
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