CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
1.5.15 Timers and Serial Port
1.5.15.1
Timer/Counter Control Register (TCON)
TCON: SFR Address $88
All bits reset to 0 on reset. This register is bit addressable.
Bit:
7
6
5
4
3
2
1
0
Timer 1
overflow
flag
(TF1)
Timer 1
run
control
(TR1)
Timer 0
overflow
flag
(TF0)
Timer 0
run
control
(TR0)
Int1 edge
flag
(IE1)
Int1 type
control
(IT1)
Int0 edge
flag
(IE0)
Int0 type
control
(IT0)
CMX850
TCON Regsiter b7: Timer 1 overflow flag (TF1)
The Timer 1 overflow flag gets set to 1 by hardware when Timer 1 overflows, and gets cleared
automatically when the Timer 1 interrupt service routine is called.
TCON Register b6: Timer 1 run control bit (TR1)
b6 = 1 Turn Timer/Counter 1 on
b6 = 0 Turn Timer/Counter 1 off
TCON Register b5: Timer 0 overflow flag (TF0)
The Timer 0 overflow flag gets set to 1 by hardware when Timer 0 overflows, and gets cleared
automatically when the Timer 0 interrupt service routine is called.
TCON Register b4: Timer 0 run control bit (TR0)
b4 = 1 Turn Timer/Counter 0 on
b4 = 0 Turn Timer/Counter 0 off
TCON Register b3: Int1 edge flag (IE1)
When Int1 is configured as falling edge triggered, this bit is set to 1 by hardware to indicate that an
edge has been detected (i.e. successive samples of the Int1 pin show a high in one machine cycle
and a low in the next cycle) and gets cleared automatically when the Int1 service routine is called.
When configured as a low level triggered interrupt, the edge flag will be updated once per cycle to
reflect the state of the Int1 pin; the flag gets set to 1 if the Int1 pin is active (i.e. low), and gets
cleared to 0 if the Int1 pin is inactive (high).
TCON Register b2: Int1 type control (IT1)
b2 = 1 Int1 configured as a falling edge triggered interrupt
b2 = 0 Int1 configured as a low level triggered interrupt.
TCON Register b1: Int0 edge flag (IE0)
When Int0 is configured as falling edge triggered, this bit is set to 1 by hardware to indicate that an
edge has been detected (i.e. successive samples of the Int0 pin show a high in one machine cycle
and a low in the next cycle) and gets cleared automatically when the Int0 service routine is called.
When configured as a low level triggered interrupt, the edge flag will be updated once per cycle to
reflect the state of the Int0 pin: the flag gets set to 1 if the Int0 pin is active (i.e. low), and gets
cleared by 0 if the Int0 pin is inactive (high).
© 2003 CML Microsystems Plc
60
D/850/6
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