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CMX850L8 View Datasheet(PDF) - CML Microsystems Plc

Part Name
Description
MFG CO.
CMX850L8
CML
CML Microsystems Plc CML
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
Line Signal
FSK signal
Teoff
DETECT Bit
Teon
(b0,CASDET)
Figure 7b FSK Level Detector Operation
1.5.13.3
FSK Demodulator
When FSK mode is selected (CASDET b6 = 1) the received signal is processed by an FSK demodulator.
What happens to the output of this demodulator depends on whether “bit” mode or “byte” mode operation is
selected.
In bit mode (CASDET b3 = 1) the demodulator output is directly connected to b7 of FSKBUF and the
interrupt status bit in the CASDET SFR is tied low (inactive). The user can therefore directly access the FSK
signal by polling b7 of the FSKBUF register.
In byte mode (CASDET b3 = 0) the FSKBUF register will be indeterminate until the FSK retiming logic has
extracted a valid character (8 data bits framed by a start and a stop bit). When a valid character has been
received, the 8 data bits are loaded into FSKBUF and the interrupt status bit in the CASDET SFR goes
high, which also asserts the Int2 signal to the 8051 µC. This alerts the user to read the FSKBUF register. As
soon as FSKBUF has been read by the 8051 µC, the interrupt is immediately cleared, and the FSKBUF
register will again become indeterminate until the next character is received. It should be noted that for
correct operation it is necessary to read the FSKBUF register within approximately 8.3ms (the time of a
complete character at 1200 baud) otherwise the data will be lost and replaced by the next valid byte of data.
If byte mode is enabled during an FSK Channel Seizure signal (a sequence of alternating mark and space
bits) it will interpret the signal as valid receive characters, with values of 55 (hex). Similarly it may interpret
speech or other signals as random characters.
1.5.13.4
Detect Control Register (CASDET)
CASDET: SFR Address $E9
All Bits are cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
Detector
Enable
Mode = CAS (0)
CAS Tone Detect Window
Control
CAS
Interrupt
clear
Interrupt
status
Detect
Mode = FSK (1)
0
0
Bit
0
Mode
Select
CASDET Register b7: Detector enable
This bit is used to enable the CAS/FSK detector circuit, and to power up the VBIAS generator and
line input amplifier in the modem circuit (if not already powered up).
© 2003 CML Microsystems Plc
54
D/850/6
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