Communications Controller
CMX850
b7 = 1 Enable detector
b7 = 0 Disable and powersave the detector
CASDET Register b6: Mode Select
This bit is used to select either CAS Tone Alert Mode or FSK Receiver Mode. The state of this bit
determines the function of the remaining bits in this register.
b6 = 1 FSK Receiver Mode
b6 = 0 CAS Tone Alert Mode
CASDET Register b5-3 (In CAS Mode): Tone Detect Window Control
CASDET Register b5-3 (In FSK Mode): Bit Mode Select
In CAS mode, the tones being detected are required to last between certain time limits before being
considered as valid CAS tones. This time window can be programmed by these register bits to give
nominal values, as shown below. The detect window will always start at 65 ms but can be
configured to finish between 100 ms and 135 ms in 5 ms divisions.
In FSK mode these bits are used to configure the FSK demodulator into bit mode or byte mode (see
description in section 1.5.13.3).
CAS MODE
b5 b4 b3
000
001
010
011
100
101
110
111
Valid Detect Tone Length 65 – 100 ms
Valid Detect Tone Length 65 – 105 ms
Valid Detect Tone Length 65 – 110 ms
Valid Detect Tone Length 65 – 115 ms
Valid Detect Tone Length 65 – 120 ms
Valid Detect Tone Length 65 – 125 ms
Valid Detect Tone Length 65 – 130 ms
Valid Detect Tone Length 65 – 135 ms
FSK MODE
b5 b4 b3
000
001
FSK byte mode
FSK bit mode
CASDET Register b2 (In CAS Mode): CAS interrupt clear
CASDET Register b2 (In FSK Mode): Unused, set to 0
In CAS mode, writing a 1 to this bit generates a short pulse that clears CASDET bit 1 (CAS
interrupt status). CASDET bit 2 always reads back as a 0.
CASDET Register b1: Interrupt status (read-only)
In CAS Tone Alert mode this bit indicates whether CAS tones of the correct duration have been
received. In FSK Receive mode it indicates that a complete byte is ready to read from FSKBUF
(assuming byte mode has been selected). The inverse of this bit is used to drive the (active low)
Int2 interrupt line to the 8051 µC. The Interrupt status bit cannot be written directly by the 8051 µC,
but it can be cleared by writing a 1 to CASDET bit 2 in CAS Tone Alert Mode, or by reading the
FSKBUF register in FSK Mode. The 8051 µC can enable or disable the the interrupt by setting or
clearing the Int2 enable bit (IE_1 bit 0).
b1 = 1 Interrupt active (CAS tone detected with correct duration or FSK byte ready)
b1 = 0 Interrupt inactive
© 2003 CML Microsystems Plc
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