CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
RTCCON Register b5: Time interrupt clear
Writing a 1 to this bit clears RTCCON bit 4 (time interrupt status). RTCCON bit 5 always reads
back as a 0.
RTCCON Register b4: Time interrupt status
This bit indicates whether a time interrupt has occurred. Its inverse is used to drive the (active low)
Int6 interrupt line to the 8051 µC. The time interrupt status bit cannot be written directly by the 8051
µC, but it can be cleared by writing a 1 to RTCCON bit 5. If the time interrupt feature is not required,
it should be disabled by clearing the time interrupt enable bit (IE_1 bit 4), and RTCCON bit 4 should
be ignored.
b4 = 1 Selected time interval has elapsed, time interrupt active
b4 = 0 Time interrupt inactive
RTCCON Register b3: Clock disable
This bit can be used to prevent the main RTC time counter from incrementing. This is
recommended when setting the TIME0/1/2/3 registers to prevent them from incrementing while
being set. This bit does not affect the internal fractions of a second prescaler or the time interval
interrupts. This bit is not affected by a reset; when the CMX850 powers up its value is unknown and
it should be set or cleared as required.
b3 = 1 Prevent the RTC TIME registers from incrementing
b3 = 0 Allow the RTC TIME registers to increment
RTCCON Register b2-0: Time IRQ Interval Select
These 3 bits select the frequency of time interrupt requests.
b2 b1 b0
0 0 0 Sixteenth of a second interval
0 0 1 Eighth of a second interval
0 1 0 Quarter of a second interval
0 1 1 Half of a second interval
1 0 0 One second interval
1 0 1 Two second interval
1 1 0 Four second interval
1 1 1 Eight second interval
1.5.12.2
RTC Time Registers (TIME0-TIME3)
The RTC stores the time in four SFRs: TIME0, TIME1, TIME2 and TIME3. Each register holds eight bits,
with TIME0 holding the least significant eight bits and TIME3 holding the most significant eight bits.
RTC TIME0: SFR Address $FC
All bits unaffected by reset.
Bit:
7
6
5
4
3
2
1
0
Bits 7 - 0 of RTC TIME register
© 2003 CML Microsystems Plc
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