CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
WDTCON Register b6-5: WDT prescale
These two bits are used to select the division ratio for the 32.768kHz clock prescaler which drives
the watchdog timeout counter.
b6 b5
0 0 Divide by 256
0 1 Divide by 64
1 0 Divide by 8
1 1 Divide by 1
WDTCON Register b4: Delayed reset enable
This bit is used to select whether a reset is generated immediately upon a WDT timeout, or whether
an interrupt request is first generated. In either mode the timeout status bit is set when the timeout
counter overflows and is only cleared by refreshing the WDT.
b4 = 1 Generate interrupt upon WDT timeout, then reset if the overflow is not
subsequently cleared
b4 = 0 Generate reset upon WDT timeout
WDTCON Register b3: Unused, set to 0
WDTCON Register b2: Timeout status
The timeout status bit is set to 1 immediately that a WDT timeout occurs. It is not affected by a
reset, but is cleared to 0 when the CMX850 first powers up (all other bits of WDTCON are cleared
upon reset). This allows the software to determine whether a system reset was the result of a WDT
timeout, so that appropriate action may be taken. Software can only clear the timeout status bit by
refreshing the WDT.
b2 = 1 Timeout counter has overflowed
b2 = 0 No timeout has occurred
WDTCON Register b1: Refresh
Writing a 1 to this bit refreshes the WDT counter, i.e. it copies the value in the WDTLD register into
the most significant eight bits of the WDT timeout counter, and sets the least significant eight bits to
$00. Also, if the timeout status bit (WDTCON.2) happens to be 1, refreshing the WDT causes it to
be cleared to 0. The refresh bit in the WDTCON register is automatically cleared to 0 after the
refresh has happened, which occurs on the first edge of the 32.768kHz clock after the refresh bit is
set to a 1.
WDTCON Register b0: Start
The bit is used to start or stop the WDT. To start the WDT, the WDTCON enable bit must be set to
1 and the 32.768kHz reference clock must be running.
b0 = 1 Start the WDT
b0 = 0 Stop the WDT
© 2003 CML Microsystems Plc
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D/850/6
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