CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
(19*100/255) = 7.45%. The PWM blocks can be used as simple D/A converters by smoothing the outputs
with suitable off-chip low-pass filters.
The contents of the PWM1 or PWM2 registers are sampled only at the beginning of each cycle of the output
square wave. The microcontroller is therefore able to update the PWM1 and PWM2 registers at any time
without affecting the current cycle; the change will only be seen after the current cycle has completed.
1.5.7.1 PWM Control Register (PWMCON)
PWMCON: SFR Address $DD
Bits b7-6 are cleared to 0 on reset. Other bits are unused, and are 0.
Bit:
7
6
5
4
3
2
1
0
PWM2
enable
PWM1
enable
Unused, always read as 0
PWMCON Register b7: PWM 2 Enable
b7 = 1 Enable PWM 2
b7 = 0 Disable and reduce power PWM 2
PWMCON Register b6: PWM 1 Enable
b6 = 1 Enable PWM 1
b6 = 0 Disable and reduce power PWM 1
PWMCON Register b5-0: Unused
1.5.7.2 PWM Data Registers (PWM1, PWM2)
PWM1: SFR Address $DE
All bits cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
Duty cycle for PWM 1
PWM2: SFR Address $DF
All bits cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
Duty cycle for PWM 2
© 2003 CML Microsystems Plc
35
D/850/6
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