CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
ADCCON1: SFR Address $E2
All bits cleared to 0 on reset.
Bit:
7
6
5
4
3
2
1
0
Threshold
high
interrupt
clear
Threshold
high
interrupt
status
Threshold
low
interrupt
clear
Threshold
low
interrupt
status
Inverted
threshold
mode
VREF
control
Continuous
convert
enable
Manual
start &
status
ADCCON1 Register b7: Threshold high Interrupt clear
Writing a 1 to this bit clears ADCCON1 bit 6 (threshold high interrupt status). ADCCON1 bit 7
always reads back as a 0.
ADCCON1 Register b6: Threshold high interrupt status
At the end of each ADC conversion, bits 9-2 of the ADC output data are compared against the
contents of the ADCTHRH register. Depending on the results of this comparison (see the
description of the inverted threshold mode bit, ADCCON1 bit 3), this may cause the threshold high
interrupt status bit to be set to 1. If this happens, the Int5 interrupt input of the 8051 µC is asserted
(pulled low). Because both the threshold high and low interrupt bits are combined to drive a single
interrupt line to the 8051 µC, this bit must be examined by software if it is necessary to determine
which of the two threshold comparators caused the interrupt. The threshold high interrupt status bit
is read-only, and can only be cleared by writing 1 to ADCCON1 bit 7.
b6 = 1 Threshold high interrupt active
b6 = 0 Threshold high interrupt inactive
ADCCON1 Register b5: Threshold low interrupt clear
Writing a 1 to this bit clears ADCCON1 bit 4 (threshold low interrupt status). ADCCON1 bit 5
always reads back as a 0.
ADCCON1 Register b4: Threshold low interrupt status
At the end of each ADC conversion, bits 9-2 of the ADC output data are compared against the
contents of the ADCTHRL register. Depending on the results of this comparison (see the description
of the inverted threshold mode bit, ADCCON1 bit 3), this may cause the threshold low interrupt
status bit to be set to 1. If this happens, the Int5 interrupt input of the 8051 µC is asserted (pulled
low). Because both the threshold high and low interrupt bits are combined to drive a single interrupt
line to the 8051 µC, this bit must be examined by software if it is necessary to determine which of
the two threshold comparators caused the interrupt. The threshold low interrupt status bit is read-
only and can only be cleared by writing 1 to ADCCON1 bit 5.
b4 = 1 Threshold low interrupt active
b4 = 0 Threshold low interrupt inactive
© 2003 CML Microsystems Plc
37
D/850/6
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