CMX850L8 View Datasheet(PDF) - CML Microsystems Plc
Part Name
Description
MFG CO.
'CMX850L8' PDF : 103 Pages View PDF
Communications Controller
CMX850
1.5.6.2 Speed Control Register (SPDCON)
The 8051 µC can be configured to run at a reduced internal clock speed, selectable through the SPDCON
register, to allow software to continue executing but with substantially reduced power consumption. This is
especially useful when combined with the low power RC oscillator option. Note that the 8051 µC clock
speed reduction does not alter the speed of the system clock used by the modem, A/D converter, or PWM
blocks, but these blocks can be separately power saved if necessary. Running the µC with a reduced clock
speed will have a direct effect on the operation of the 8051 core’s interrupt latency, serial port, and timers.
The 8051 µC clock can be selected to be a simple binary division of the main system clock, with division
ratios selectable between ÷4 and ÷1024. However, because many external memory devices only enter low
power standby mode when they are not being accessed, this simple binary division may not achieve the
ultimate power saving possible. This is because the average time that the external memory is being
accessed will not reduce. The 8051 µC speed control mechanism can therefore be configured into a new
“burst mode”, where the µC executes single complete instructions at a time at full speed, followed by longer
periods of inactivity where the clock to the µC is halted and external memory is held in standby (CSN1/2/3
and OEN pins held high). The average instruction throughput in burst mode is identical to that in non-burst
mode, but the average time for which the external memory is active is greatly reduced.
When in reduced speed mode or power down mode, the external data bus may float for considerable
periods of time. This may cause unnecessary power consumption in devices connected to the data bus due
to voltage drift on the bus pins. To avoid this, the memory interface can be configured with weak bus-
holding devices to prevent this voltage drift (see description of MEMCON register).
The 8051 µC can be configured, using the SPXMASK register, to exit reduced speed mode automatically
upon receiving an interrupt signal. This immediately causes the 8051 µC to begin clocking again at full
speed.
SPDCON: SFR Address $9D
All bits cleared to 0 on reset, or upon automatic exit of reduced speed operation.
Bit:
7
6
5
4
3
2
1
0
Unused, always read as 0
Burst
mode
8051 µC clock speed select
SPDCON Register b7-4: Unused
SPDCON Register b3: Burst mode
b3 = 1 Burst mode enabled
b3 = 0 Burst mode disabled
© 2003 CML Microsystems Plc
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