EVAL-AD1938AZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD1938AZ' PDF : 32 Pages View PDF
AD1928
CONTROL REGISTERS
DEFINITIONS
The format is the same for I2C and SPI ports. The global address for the AD1928 is 0x04, shifted left one bit due to the R/W bit. All
registers are reset to 0, except for the DAC volume registers that are set to full volume. Note that the first setting in each control register
parameter is the default setting.
Table 14. Register Format
Global Address
R/W
Bit
23:17
16
Register Address
15:8
Data
7:0
Table 15. Register Addresses and Functions
Address
Function
0
PLL and Clock Control 0
1
PLL and Clock Control 1
2
DAC Control 0
3
DAC Control 1
4
DAC Control 2
5
DAC individual channel mutes
6
DAC 1L volume control
7
DAC 1R volume control
8
DAC 2L volume control
9
DAC 2R volume control
10
DAC 3L volume control
11
DAC 3R volume control
12
DAC 4L volume control
13
DAC 4R volume control
14
ADC Control 0
15
ADC Control 1
16
ADC Control 2
PLL AND CLOCK CONTROL REGISTERS
Table 16. PLL and Clock Control 0 Register
Bit
Value
Function
0
0
Normal operation
1
Power-down
2:1
00
Input 256 (×44.1 kHz or 48 kHz)
01
Input 384 (×44.1 kHz or 48 kHz)
10
Input 512 (×44.1 kHz or 48 kHz)
11
Input 768 (×44.1 kHz or 48 kHz)
4:3
00
XTAL oscillator enabled
01
256 × fS VCO output
10
512 × fS VCO output
11
Off
6:5
00
MCLKI/XI
01
DLRCLK
10
ALRCLK
11
Reserved
7
0
Disable: ADC and DAC idle
1
Enable: ADC and DAC active
Description
PLL power-down
MCLKI/XI pin functionality (PLL active), master clock rate setting
MCLKO/XO pin, master clock rate setting
PLL input
Internal master clock enable
Rev. 0 | Page 24 of 32
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