AD1928
Table 25. ADC Control 2 Register
Bit
Value
Function
0
0
50/50 (allows 32, 24, 20, 16 bit clocks (BCLKs) per
channel
1
Pulse (32 BCLKs per channel)
1
0
Drive out on falling edge (DEF)
1
Drive out on rising edge
2
0
Left low
1
Left high
3
0
Slave
1
Master
5:4
00
64
01
128
10
256
11
512
6
0
Slave
1
Master
7
0
ABCLK pin
1
Internally generated
Description
LRCLK format
BCLK polarity
LRCLK polarity
LRCLK master/slave
BCLKs per frame
BCLK master/slave
BCLK source
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