EVAL-AD1938AZ View Datasheet(PDF) - Analog Devices
Part Name
Description
MFG CO.
'EVAL-AD1938AZ' PDF : 32 Pages View PDF
Table 17. PLL and Clock Control 1 Register
Bit Value Function
00
PLL clock
1
MCLK
10
PLL clock
1
MCLK
20
Enabled
1
Disabled
30
Not locked
1
Locked
7:4 0000
Reserved
Description
DAC clock source select
ADC clock source select
On-chip voltage reference
PLL lock indicator (read only)
DAC CONTROL REGISTERS
Table 18. DAC Control 0 Register
Bit Value Function
00
Normal operation
1
Power-down
2:1 00
32 kHz/44.1 kHz/48 kHz
01
64 kHz/88.2 kHz/96 kHz
10
128 kHz/176.4 kHz/192 kHz
11
Reserved
5:3 000
1
001
0
010
8
011
12
100
16
101
Reserved
110
Reserved
111
Reserved
7:6 00
Stereo (normal)
01
TDM (daisy chain)
10
DAC AUX mode (ADC-, DAC-, TDM-coupled)
11
Dual-line TDM
Description
Power-down
Sample rates
SDATA delay (BCLK periods)
Serial format
Table 19. DAC Control 1 Register
Bit Value Function
00
Latch in midcycle (normal)
1
Latch in at end of cycle (pipeline)
2:1 00
64 (2 channels)
01
128 (4 channels)
10
256 (8 channels)
11
512 (16 channels)
30
Left low
1
Left high
40
Slave
1
Master
50
Slave
1
Master
60
DBCLK pin
1
Internally generated
70
Normal
1
Inverted
Description
BCLK active edge (TDM in)
BCLKs per frame
LRCLK polarity
LRCLK master/slave
BCLK master/slave
BCLK source
BCLK polarity
Rev. 0 | Page 25 of 32
AD1928
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