ADC CONTROL REGISTERS
Table 23. ADC Control 0 Register
Bit
Value
Function
0
0
Normal operation
1
Power down
1
0
Off
1
On
2
0
Reserved
3
0
Reserved
4
0
Unmute
1
Mute
5
0
Unmute
1
Mute
7:6
00
32 kHz/44.1 kHz/48 kHz
01
64 kHz/88.2 kHz/96 kHz
10
128 kHz/176.4 kHz/192 kHz
11
Reserved
Table 24. ADC Control 1 Register
Bit
Value
Function
1:0
00
24
01
20
10
Reserved
11
16
4:2
000
1
001
0
010
8
011
12
100
16
101
Reserved
110
Reserved
111
Reserved
6:5
00
Stereo
01
TDM (daisy chain)
10
ADC AUX mode (ADC-, DAC-, TDM-coupled)
11
Reserved
7
0
Latch in midcycle (normal)
1
Latch in at end of cycle (pipeline)
Description
Power-down
High-pass filter
ADC 1L mute
ADC 1R mute
Output sample rate
Description
Word width
SDATA delay (BCLK periods)
Serial format
BCLK active edge (TDM in)
AD1928
Rev. 0 | Page 27 of 32