FDC37N869 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
FDC37N869
SMSC -> Microchip
'FDC37N869' PDF : 147 Pages View PDF
Command Busy, Bit 4
This bit is set to a “1” when a command is in progress. This bit will go active after the command byte has been
accepted and goes inactive at the end of the results phase. If there is no result phase (Seek, Recalibrate
commands), this bit is returned to a “0” after the last command byte.
Non-DMA, Bit 5
This mode is selected in the SPECIFY command and will be set to a “1” during the execution phase of a
command. This is for polled data transfers and helps to differentiate between the data transfer phase and the
reading of result bytes.
DIO, Bit 6
Indicates the direction of a data transfer once an RQM is set. A “1” indicates a read and a “0” indicates a write is
required.
RQM, Bit 7
Indicates that the host can transfer data if set to a “1”. No access is permitted if set to a “0”.
DATA RATE SELECT REGISTER (DSR)
The Data Rate Select Register (Base Address + 4: Write-only) is used to program the data rate, amount of write
precompensation, power down status, and software reset (Table 17). Note: the data rate is programmed using
the Configuration Control Register (CCR) not the DSR, for PC/AT and PS/2 Model 30 and Microchannel
applications. Other applications can set the data rate in the DSR. The data rate of the floppy controller is the most
recent write of either the DSR or CCR. The DSR is unaffected by a software reset. A hardware reset will set the
DSR to 02H, which corresponds to the default precompensation setting and 250 Kbps.
RESET
CONDITION
7
S/W
RESET
0
Table 17 - Data Rate Select Register
6
5
4
3
2
POWER
DOWN
0 PRE- PRE- PRE-
COMP2 COMP1 COMP0
0
0
0
0
0
1
DRATE
SEL1
1
0
DRATE
SEL0
0
Data Rate Select, Bits 0 - 1
These bits control the data rate of the floppy controller. See Table 19 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset and are set to 250 Kbps after a
hardware reset.
Precompensation Select, Bits 2 - 4
These three bits select the value of write precompensation that will be applied to the WDATA output signal.
Table 18 shows the precompensation values for the combination of these bits settings. Track 0 is the default
starting track number to start precompensation. The starting track number can be changed using the Configure
command.
Undefined, Bit 5
Should be written as a logic “0”.
SMSC DS – FDC37N869
Page 26
Rev. 11/09/2000
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