FDC37N869 View Datasheet(PDF) - SMSC -> Microchip
Part Name
Description
MFG CO.
FDC37N869
SMSC -> Microchip
'FDC37N869' PDF : 147 Pages View PDF
PS/2 Interface Mode
RESET
CONDITION
7
DSK CHG
N/A
Table 24 - DIR PS/2 Interface Mode
6
5
4
3
2
1
1
1
1
DRATE
SEL1
N/A N/A N/A N/A
N/A
1
DRATE
SEL0
N/A
0
nHIGH
DENS
1
nHIGH DENS, Bit 0
This bit is low whenever the 500 Kbps or 1 Mbps data rates are selected, and high when 250 Kbps and 300 Kbps
are selected.
Data Rate Select, Bits 1 - 2
These bits control the data rate of the floppy controller. See Table 19 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250 Kbps after a
hardware reset.
Undefined, Bits 3 - 6
Always read as a logic “1”
DSK CHG, Bit 7
The DSK CHG bit monitors the pin of the same name and reflects the opposite value seen on the disk cable. The
DSK CHG bit also depends upon the Force Disk Change bits in the Force FDD Status Change register (see
section CR17 on page 109).
Model 30 Interface Mode
RESET
CONDITION
7
DSK CHG
N/A
Table 25 - DIR Model 30 Interface Mode
65
4
3
2
00
0
DMAEN NOPREC
00
0
0
0
1
0
DRATE SEL1 DRATE SEL0
1
0
Data Rate Select, Bits 0 - 1
These bits control the data rate of the floppy controller. See Table 19 for the settings corresponding to the
individual data rates. The data rate select bits are unaffected by a software reset, and are set to 250kb/s after a
hardware reset
Noprec, Bit 2
This bit reflects the value of the NOPREC bit set in the CCR register.
DMAEN, Bit 3
This bit reflects the value of DMAEN bit set in the DOR register bit 3.
Undefined, Bits 4 - 6
Always read as a logic “0”
SMSC DS – FDC37N869
Page 30
Rev. 11/09/2000
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