HT47C20L View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT47C20L' PDF : 55 Pages View PDF
HT47C20L
The states of the registers are summarized in the following table:
Register
Reset
(power on)
WDT time-out
RES reset
(normal Operation) (normal operation)
TMRAH
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMRAL
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMRC
0000 1---
0000 1---
0000 1---
TMRBH
xxxx xxxx
xxxx xxxx
xxxx xxxx
TMRBL
xxxx xxxx
xxxx xxxx
xxxx xxxx
ADCR
1xxx --00
1xxx --00
1xxx --00
Program
Counter
000H
000H
000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuu uuuu
TBLH
xxxx xxxx
uuuu uuuu
uuuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
INTC0
-000 0000
-000 0000
-000 0000
INTC1
---0 ---0
---0 ---0
---0 ---0
RTCC
--xx 0111
--xx 0111
--xx 0111
PA
1111 1111
1111 1111
1111 1111
Note: ²*² refers to ²warm reset²
²u² means ²unchanged²
²x² means ²unknown²
RES reset
(HALT)
xxxx xxxx
xxxx xxxx
0000 1---
xxxx xxxx
xxxx xxxx
1xxx --00
000H
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--01 uuuu
-000 0000
---0 ---0
--xx 0111
1111 1111
WDT time-out
(HALT)
uuuu uuuu
uuuu uuuu
uuuu u---
uuuu uuuu
uuuu uuuu
uuuu --uu
000H*
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
--11 uuuu
-uuu uuuu
---u ---u
--uu uuuu
uuuu uuuu
Timer/Event Counter
One 16-bit timer/event counter with PFD output or two
channels of RC type A/D converter is implemented in
the HT47C20L. The ADC/TM bit (bit 1 of ADCR register)
decides whether timer A and timer B are composed of
one 16-bit timer/event counter or timer A and timer B are
composed of two channels RC type A/D converter.
The TMRAL, TMRAH, TMRBL, TMRBH composed of one
16-bit timer/event counter, when ADC/TM bit is ²0². The
TMRBL and TMRBH are timer/event counter preload
registers for lower-order byte and higher-order byte re-
spectively.
The timer/event counter clock source may come from
system clock or T1 (system clock/4) or real time clock
time-out signal or external source.
Using external clock input allows the user to count exter-
nal events, count external RC type A/D clock, measure
time intervals or pulse widths, or generate an accurate
time base. While using the internal clock allows the user
to generate an accurate time base.
There are six registers related to the timer/event counter
operating mode. TMRAH ([20H]), TMRAL ([21H]), TMRC
([22H]), TMRBH ([23H]), TMRBL ([24H]) and ADCR
([25H]). Writing to TMRBL only writes the data into a low
S y s te m C lo c k
T1
A /D C lo c k
R e a l T im e C lo c k O u tp u t
M
U
TM R 0
X
D a ta B u s
1 6 - b it T im e r A
O v e r flo w T Q
PFD
R
TE
TM 2
P u ls e W id th
TM 1
TM 0
TO N
M e a s u re m e n t
M o d e C o n tro l
TM 2
TM 1
TM 0
1 6 - b it T im e r B
R e lo a d
P A 3 D a ta C T R L
Timer/Event Counter
Rev. 2.30
15
December 2, 2005
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