HT47C20L View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT47C20L' PDF : 55 Pages View PDF
HT47C20L
Bit No.
0~2
3
4
5
6
7
Label
¾
TE
TON
TM0
TM1
TM2
Function
Unused bit, read as ²0²
To define the TMR active edge of the timer/event counter
(0= active on low to high; 1= active on high to low)
To enable/disable timer counting (0= disabled; 1= enabled)
To define the operating mode (TM2, TM1, TM0)
000= Timer mode (system clock)
001= Timer mode (system clock/4)
010= Timer mode (real time clock output)
011= A/D clock mode (RC oscillation decided by ADCR register)
100= Event counter mode (external clock)
101= Pulse width measurement mode (system clock/4)
110= Unused
111= Unused
TMRC (22H) Register
byte buffer, and writing to TMRBH will write the data and
the contents of the low byte buffer into the time/event
counter preload register (16-bit) simultaneously. The
timer/event counter preload register is changed by writ-
ing to TMRBH operations and writing to TMRBL will keep
the timer/event counter preload register unchanged.
Reading TMRAH will also latch the TMRAL into the low
byte buffer to avoid the false timing problem. Reading
TMRAL returns the contents of the low byte buffer. In
other words, the low byte of the timer/event counter can
not be read directly. It must read the TMRAH first to
make the low byte contents of timer/event counter be
latched into the buffer.
If the timer/event counter is on, the TMRAH, TMRAL,
TMRBH and TMRBL cannot be read or written to. To
avoid conflicting between timer A and timer B, the
TMRAH, TMRAL, TMRBH and TMRBL registers
should be accessed with ²MOV² instruction under
timer off condition.
The TMRC is the timer/event counter control register,
which defines the timer/event counter options.
The timer/event counter control register define the oper-
ating mode, counting enable or disable and active edge.
Writing to timer B location puts the starting value in the
timer/event counter preload register, while reading timer
A yields the contents of the timer/event counter. Timer B
is timer/event counter preload register.
The TM0, TM1 and TM2 bits define the operation mode.
The event count mode is used to count external events,
which means that the clock source comes from an exter-
nal (TMR) pin. The A/D clock mode is used to count ex-
ternal A/D clock, the RC oscillation mode is decided by
ADCR register. The timer mode functions as a normal
timer with the clock source coming from the internal se-
lected clock source. Finally, the pulse width measure-
ment mode can be used to count the high or low level
duration of the external signal (TMR). The counting is
based on the T1 (system clock/4).
In the event count, A/D clock or internal timer mode,
once the timer/event counter starts counting, it will count
from the current contents in the timer/event counter
(TMRAH and TMRAL) to FFFFH. Once overflow occurs,
the counter is reloaded from the timer/event counter
preload register (TMRBH and TMRBL) and generates
the corresponding interrupt request flag (TF; bit 4 of
INTC1) at the same time.
In the pulse width measurement mode with the TON
and TE bits equal to 1, once the TMR has received a
transient from low to high (or high to low if the TE bit is
0) it will start counting until the TMR returns to the origi-
nal level and resets the TON. The measured result will
remain in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it re-
ceives further transient pulse. Note that in this operation
mode, the timer/event counter starts counting not ac-
cording to the logic level but according to the transient
edges. In the case of counter overflow, the counter is re-
loaded from the timer/event counter preload register
and issues interrupt request just like the other three
modes.
To enable the counting operation, the timer On bit (TON;
bit 4 of TMRC) should be set to 1. In the pulse width
measurement mode, the TON will automatically be
cleared after the measurement cycle is completed. But
in the other three modes, the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources and can also be applied as
a PFD (programmable frequency divider) output at PA3
by mask option. No matter what the operation mode is,
writing a 0 to ETI can disable the corresponding inter-
rupt service. When the PFD function is selected, execut-
ing ²CLR PA.3² instruction to enable the PFD output and
executing ²SET PA.3² instruction to disable the PFD
output and PA.3 output low level.
Rev. 2.30
16
December 2, 2005
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