HT47C20L View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT47C20L' PDF : 55 Pages View PDF
HT47C20L
A/D Converter
Two channels of RC type A/D converter are imple-
mented in the HT47C20L. The A/D converter contains
two 16-bit programmable count-up counter and the
timer A clock source may come from the system clock,
T1 (system clock/4) or real time clock output. The timer
B clock source may come from the external RC oscilla-
tor. The TMRAL, TMRAH, TMRBL, TMRBH are composed
of the A/D converter when ADC/TM bit (bit 1 of ADCR regis-
ter) is ²1².
The A/D converter timer B clock source may come from
channel 0 (IN0 external clock input mode, RS0~CS0 os-
cillation, RT0~CS0 oscillation, CRT0~CS0 oscillation
(CRT0 is a resistor), or RS0~CRT0 oscillation (CRT0 is
a capacitor) or channel 1 (RS1~CS1 oscillation,
RT1~CS1 oscillation or IN1 external clock input). The
timer A clock source is from the system clock, T1 or real
time clock prescaler clock output decided by TMRC reg-
ister.
There are six registers related to A/D converter, i.e.,
TMRAH, TMRAL, TMRC, TMRBH, TMRBL and ADCR.
The internal timer clock is input to TMRAH and TMRAL,
the A/D clock is input to TMRBH and TMRBL. The
OVB/OVA bit (bit 0 of the ADCR register) decides
whether timer A overflows or timer B overflows, then the
TF bit is set and timer interrupt occurs. When the A/D
converter mode timer A or timer B overflows, the TON bit
is reset and stop counting. Writing TMRAH/TMRBH puts
the starting value in the timer A/timer B and reading
TMRAH/TMRBH gets the contents of the timer A/timer
B. Writing TMRAL/TMRBL only writes the data into a low
byte buffer, and writing TMRAH/TMRBH will write the
data and the contents of the low byte buffer into the
timer A/timer B (16-bit) simultaneously. The timer
A/timer B is change by writing TMRAH/TMRBH opera-
tions and writing TMRAL/TMRBL will keep the timer
A/timer B unchanged.
Reading TMRAH/TMRBH will also latch the
TMRAL/TMRBL into the low byte buffer to avoid the
false timing problem. Reading TMRAL/TMRBL returns
the contents of the low byte buffer. In other word, the low
byte of timer A/timer B can not be read directly. It must
read the TMRAH/TMRBH first to make the low byte con-
tents of timer A/timer B be latched into the buffer.
If the A/D converter timer A and timer B are count-
ing, the TMRAH, TMRAL, TMRBH and TMRBL can-
not be read or written to. To avoid conflicting
between timer A and timer B, the TMRAH, TMRAL,
TMRBH and TMRBL registers should be accessed
with ²MOV² instruction under timer A and timer B off
condition.
The bit4~bit7 of ADCR decides which resistor and ca-
pacitor compose an oscillation circuit and input to
TMRBH and TMRBL.
The TM0, TM1 and TM2 bits of TMRC define the clock
source of timer A. It is suggested that the clock source of
timer A use the system clock, instruction clock or real
time clock prescaler clock.
The TON bit (bit 4 of TMRC) is set ²1², the timer A and
timer B will start counting until timer A or timer B over-
flows, the timer/event counter generates the interrupt re-
quest flag (TF ; bit 4 of INTC1) and the timer A and timer
B stop counting and reset the TON bit to ²0² at the same
time.
If the TON bit is ²1², the TMRAH, TMRAL, TMRBH
and TMRBL cannot be read or written to. Only when
the timer/event counter is off and when the instruc-
tion ²MOV² is used could those four registers be
read or written to.
Rev. 2.30
18
December 2, 2005
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