HT48R065G View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48R065G' PDF : 126 Pages View PDF
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Operating Mode Control
· HT48R064G/HT48R065G/HT48R066G
Operating
Mode
Normal
Slow
Sleep
HXT
Run
¾
Stop
OSC1/OSC2 Configuration
ERC
HIRC
HIRC + LXT
HIRC
LXT
Run
Run
Run
Run
¾
¾
Stop
Run
Stop
Stop
Stop
Run
²¾² unimplemented
· HT48R0662G
Operating
Mode
Normal
Slow
Idle
Sleep
OSC1/OSC2 Configuration
HXT
ERC
HIRC
Run
Stop
Stop
Stop
Run
Stop
Stop
Stop
Run
Stop
Stop
Stop
OSC3/OSC4 Configuration
LXT
LXTEN=0
LXTEN=1
Run
Run
Run
Run
Stop
Run
Stop
Stop
Mode Switching
The devices are switched between one mode and another using a combination of the CLKMOD bit in
the CTRL0 register and the HALT instruction. The CLKMOD bit chooses whether the system runs in
either the Normal or Slow Mode by selecting the system clock to be sourced from either a high or low
frequency oscillator. The HALT instruction forces the system into either the Idle or Sleep Mode,
depending upon whether the LXT oscillator is running or not. The HALT instruction operates
independently of the CLKMOD bit condition.
When a HALT instruction is executed and the LXT oscillator is not running, the system enters the
Sleep mode the following conditions exist:
· The system oscillator will stop running and the application program will stop at the ²HALT²
instruction.
· The Data Memory contents and registers will maintain their present condition.
· The WDT will be cleared and resume counting if the WDT clock source is selected to come from the
LIRC or LXT oscillator. The WDT will stop if its clock source originates from the system clock.
· The I/O ports will maintain their present condition.
· In the status register, the Power Down flag, PDF, will be set and the Watchdog time-out flag, TO,
will be cleared.
Rev. 1.10
42
October 23, 2012
Share Link: 
