HT48R065G View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48R065G' PDF : 126 Pages View PDF
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
Standby Current Considerations
As the main reason for entering the Idle/Sleep Mode is to keep the current consumption of the MCU to
as low a value as possible, perhaps only in the order of several micro-amps, there are other
considerations which must also be taken into account by the circuit designer if the power consumption
is to be minimised.
Special attention must be made to the I/O pins on the device. All high-impedance input pins must be
connected to either a fixed high or low level as any floating input pins could create internal oscillations
and result in increased current consumption. Care must also be taken with the loads, which are
connected to I/O pins, which are setup as outputs. These should be placed in a condition in which
minimum current is drawn or connected only to external circuits that do not draw current, such as other
CMOS inputs.
If the configuration options have enabled the LIRC oscillator, then this will continue to run when in the
Idle/Sleep Mode and will thus consume some power. For power sensitive applications it may be
therefore preferable to use the system clock source for the Watchdog Timer. The LXT, if configured for
use, will also consume a limited amount of power, as it continues to run when the device enters the
Idle/Sleep Mode. To keep the LXT power consumption to a minimum level the LXTLP bit in the
CTRL0 register, which controls the low power function, should be set high.
Wake-up
After the system enters the Idle/Sleep Mode, it can be woken up from one of various sources listed as
follows:
· An external reset
· An external falling edge on PA0~PA7 or PC0~PC7 (HT48R0662G only)
· A system interrupt
· A WDT overflow
If the system is woken up by an external reset, the device will experience a full system reset, how-
ever, if the device is woken up by a WDT overflow, a Watchdog Timer reset will be initiated. Al-
though both of these wake-up methods will initiate a reset operation, the actual source of the
wake-up can be determined by examining the TO and PDF flags. The PDF flag is cleared by a sys-
tem power-up or executing the clear Watchdog Timer instructions and is set when executing the
²HALT² instruction. The TO flag is set if a WDT time-out occurs, and causes a wake-up that only re-
sets the Program Counter and Stack Pointer, the other flags remain in their original status.
Pins PA0 to PA7 or PC0 to PC7 can be setup via the PAWK or PCWK register to permit a negative
transition on the pin to wake-up the system. When a pin on PA0~PA7 or PC0~PC7 wake-up occurs, the
program will resume execution at the instruction following the ²HALT² instruction.
If the system is woken up by an interrupt, then two possible situations may occur. The first is where the
related interrupt is disabled or the interrupt is enabled but the stack is full, in which case the program
will resume execution at the instruction following the ²HALT² instruction. In this situation, the
interrupt which woke-up the device will not be immediately serviced, but will rather be serviced later
when the related interrupt is finally enabled or when a stack level becomes free. The other situation is
where the related interrupt is enabled and the stack is not full, in which case the regular interrupt
response takes place. If an interrupt request flag is set to ²1² before entering the Idle/Sleep Mode, then
any future interrupt requests will not generate a wake-up function and the related interrupt will be
ignored.
Rev. 1.10
43
October 23, 2012
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