HT48R065G View Datasheet(PDF) - Holtek Semiconductor
Part Name
Description
MFG CO.
'HT48R065G' PDF : 126 Pages View PDF
HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
The Watchdog Timer clock can emanate from three different sources, selected by configuration option.
These are LXT, fSYS/4, or LIRC. It is important to note that when the system enters the Idle/Sleep Mode
the instruction clock is stopped, therefore if the configuration options have selected fSYS/4 as the
Watchdog Timer clock source, the Watchdog Timer will cease to function. For systems that operate in
noisy environments, using the LIRC or the LXT as the clock source is therefore the recommended
choice. The division ratio of the prescaler is determined by bits 0, 1 and 2 of the WDTS register, known
as WS0, WS1 and WS2. If the Watchdog Timer internal clock source is selected and with the WS0, WS1
and WS2 bits of the WDTS register all set high, the prescaler division ratio will give a maximum
time-out period.
C L R W D T 1 F la g
C L R W D T 2 F la g
1 o r 2 In s tr u c tio n s
fS Y S /4
LX T
L IR C
W D T C lo c k S o u r c e S e le c tio n
C le a r W D T T y p e
C o n fig u r a tio n O p tio n
C o n fig .
O p tio n
S e le c t
fW D T C K
C LR
1 5 s ta g e c o u n te r
W S 2~W S 0
Watchdog Timer
W D T T im e - o u t
Under normal program operation, a Watchdog Timer time-out will initialise a device reset and set the
status bit TO. However, if the system is in the Idle/Sleep Mode, when a Watchdog Timer time-out
occurs, the device will be woken up, the TO bit in the status register will be set and only the Program
Counter and Stack Pointer will be reset. Three methods can be adopted to clear the contents of the
Watchdog Timer. The first is an external hardware reset, which means a low level on the external reset
pin, the second is using the Clear Watchdog Timer software instructions and the third is when a HALT
instruction is executed. There are two methods of using software instructions to clear the Watchdog
Timer, one of which must be chosen by configuration option. The first option is to use the single ²CLR
WDT² instruction while the second is to use the two commands ²CLR WDT1² and ²CLR WDT2². For
the first option, a simple execution of ²CLR WDT² will clear the Watchdog Timer while for the second
option, both ²CLR WDT1² and ²CLR WDT2² must both be executed to successfully clear the
Watchdog Timer. Note that for this second option, if ²CLR WDT1² is used to clear the Watchdog
Timer, successive executions of this instruction will have no effect, only the execution of a ²CLR
WDT2² instruction will clear the Watchdog Timer. Similarly after the ²CLR WDT2² instruction has
been executed, only a successive ²CLR WDT1² instruction can clear the Watchdog Timer.
WDTS Register
Bit
7
6
5
4
3
Name
¾
¾
¾
¾
¾
R/W
¾
¾
¾
¾
¾
POR
¾
¾
¾
¾
¾
Bit 7~3 :
Bit 2~0
unimplemented, read as ²0²
WS2, WS1, WS0: WDT time-out period selection
000: 28 tWDTCK
001: 29 tWDTCK
010: 210 tWDTCK
011: 211 tWDTCK
100: 212 tWDTCK
101: 213 tWDTCK
110: 214 tWDTCK
111: 215 tWDTCK
2
WS2
R/W
1
1
WS1
R/W
1
0
WS0
R/W
1
Rev. 1.10
45
October 23, 2012
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