HT48R064G/065G/066G/0662G
Enhanced I/O Type 8-Bit OTP MCU with OPA
No matter what the source of the wake-up event is, once a wake-up event occurs, there will be a time
delay before normal program execution resumes. Consult the table for the related time.
Wake-up
Source
External RES
PA or PC* Port
Interrupt
WDT Overflow
Oscillator Type
ERC, IRC
Crystal
tRSDT + tSST2
tRSDT + tSST2
tSST1
tSST2
²*² Port C pin wake-up is only available for the HT48R0662G device.
Note:
1. tRSTD (reset delay time), tSYS (system clock)
2. tRSTD is power-on delay, typical time=50ms
3. tSST1= 2 tSYS
4. tSST2= 128 tSYS
Wake-up Delay Time
Watchdog Timer
The Watchdog Timer, also known as the WDT, is provided to inhibit program malfunctions caused by
the program jumping to unknown locations due to certain uncontrollable external events such as
electrical noise.
Watchdog Timer Operation
It operates by providing a device reset when the Watchdog Timer counter overflows. Note that if the
Watchdog Timer function is not enabled, then any instructions related to the Watchdog Timer will
result in no operation.
Setting up the various Watchdog Timer options are controlled via the configuration options and two
internal registers WDTS and CTRL1. Enabling the Watchdog Timer can be controlled by both a
configuration option and the WDTEN bits in the CTRL1 internal register in the Data Memory.
Configuration Option
Disable
Disable
Enable
CTRL1 Register
Disable
Enable
x
WDT Function
OFF
ON
ON
Watchdog Timer On/Off Control
The Watchdog Timer will be disabled if bits WDTEN3~WDTEN0 in the CTRL1 register are written
with the binary value 1010B and WDT configuration option is disable. This will be the condition
when the device is powered up. Although any other data written to WDTEN3~WDTEN0 will ensure
that the Watchdog Timer is enabled, for maximum protection it is recommended that the value
0101B is written to these bits.
Rev. 1.10
44
October 23, 2012