KSZ8895FLXC View Datasheet(PDF) - Microchip Technology
Part Name
Description
MFG CO.
KSZ8895FLXC
Microchip Technology
'KSZ8895FLXC' PDF : 108 Pages View PDF
KSZ8895MQX/RQX/FQX/MLX
3.3 Power Management
The KSZ8895MQX/RQX/FQX/MLX supports a full chip hardware power down mode. When the PWRDN Pin 47 is inter-
nally activated low (pin PWRDN = 0), the entire chip is powered down. If this pin is de-asserted, the chip will be reset
internally.
The KSZ8895MQX/RQX/FQX/MLX can also use multiple power levels of 3.3V, 2.5V, or 1.8V for VDDIO to support dif-
ferent I/O voltage.
The KSZ8895MQX/RQX/FQX/MLX supports enhanced power management in a low power state, with energy detection
to ensure low power dissipation during device idle periods. There are five operation modes under the power manage-
ment function which are controlled by the Register 14 bit [4:3] and the Port Register Control 13 bit 3 as shown below:
Register 14 bits [4:3] = 00 Normal Operation Mode
Register 14 bits [4:3] = 01 Energy Detect Mode
Register 14 bits [4:3] = 10 Soft Power Down Mode
Register 14 bits [4:3] = 11 Power Saving Mode
The Port Register 29, 45, 61, 77, 93 Control 13 bit3 = 1 are for the Port Based Power-Down Mode.
Table 3-3 indicates all internal function blocks’ status under four different power management operation modes.
TABLE 3-3: INTERNAL FUNCTION BLOCK STATUS
Function Blocks
Normal Mode
Power Management Operation Modes
Power Saving Mode Energy Detect Mode Soft Power-Down Mode
Internal PLL Clock
Tx/Rx PHY
MAC
Host Interface
Enabled
Enabled
Enabled
Enabled
Enabled
Rx Unused Block
Disabled
Enabled
Enabled
Disabled
Energy Detect at Rx
Disabled
Disabled
Disabled
Disabled
Disabled
Disabled
3.3.1 NORMAL OPERATION MODE
This is the default setting bits [4:3] = 00 in Register 14 after chip power-up or hardware reset. When KSZ8895MQX/
RQX/FQX/MLX is in normal operation mode, all PLL clocks are running, PHY and MAC are on, and the host interface
is ready for CPU READ or WRITE.
During normal operation mode, the host CPU can set the bits [4:3] in Register 14 to change the current normal operation
mode to any one of the other three power management operation modes.
3.3.2 ENERGY DETECT MODE
Energy detect mode provides a mechanism to save more power than in the normal operation mode when the
KSZ8895MQX/RQX/FQX/MLX port is not connected to an active link partner. In this mode, the device will save more
power when the cables are unplugged. If the cable is not plugged in, the device can automatically enter a low power
state, the energy detect mode. In this mode, the device will keep transmitting 120 ns width pulses at a rate of 1 pulse
per second. Once activity resumes due to plugging a cable in or attempting by the far end to establish link, the device
can automatically power up to normal power state in energy detect mode.
Energy detect mode consists of two states, normal power state and low power state. While in low power state, the device
reduces power consumption by disabling all circuitry except the energy detect circuitry of the receiver. The energy detect
mode is entered by setting bits [4:3] = 01 in Register 14. When the KSZ8895MQX/RQX/FQX/MLX is in this mode, it will
monitor the cable energy. If there is no energy on the cable for a time longer than the pre-configured value at bit [7:0]
Go-Sleep time in Register 15, the device will go into low power state. When KSZ8895MQX/RQX/FQX/MLX is in low
power state, it will keep monitoring the cable energy.
Once the energy is detected from the cable, the device will enter normal power state. When the device is at normal
power state, it is able to transmit or receive packet from the cable.
2016 Microchip Technology Inc.
DS00002246A-page 27
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