L6238 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6238' PDF : 35 Pages View PDF
L6238
Figure 10: Phase Detector State Diagram.
must be low enough so that the motor can follow
without slipping. This implies that to have a reli-
able algorithm, the initial frequency and ramp rate
must be chosen for the worst case motor under
worst case conditions.
4.0 DIGITAL PLL MOTOR SPEED CONTROL
4.1 Phase Detector
The internal Phase/Frequency Detector of the
PLL has two inputs:
- reference input (Fref)
- feedback input (Fmtr)
The feedback Input is multiplexed between the in-
ternal Bemf Zero Crossing Detector and an exter-
nally provided sync pulse (EXT INDEX)
Shown in figure 10 is the classical state diagram
for a phase detector along with waveform exam-
ples.
Positive phase is defined as when the reference
falling edge occurs before the falling edge of
Fmotor and the motor speed must be increased.
Negative phase is just the opposite, requiring a
slowing of the motor speed.
As an example, the top four waveforms in figure
10 represent a positive phase condition. In this
case the ”up” signal would go low since the refer-
ence signal went low before the appearance of a
negative transition of fmotor. The falling edge of
fmotor causes the ”up” signal to revert back to a
high. The period while the ”up” signal is in a low
state is a function of the phase difference.
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