L6238 View Datasheet(PDF) - STMicroelectronics
Part Name
Description
MFG CO.
'L6238' PDF : 35 Pages View PDF
Figure 11: Logic Block Diagram.
L6238
4.2 Counter Section
Figure 11 is a block diagram of the counter sec-
tion of the PLL along with the phase detector.
The phase detector provides up and down signals
that are used to control the direction and counting
period of two 8 bit counters. Two counters are
used to provide both coarse and fine phase error
information. The coarse counter operates to bring
the phase error into a finite window, while the fine
counter with it’s higher resolution controls the
phase jitter to typically 5µs.
As an example, during a positive phase measure-
ment, the counters are reset to 10000000 which
is the middle of their measurement range corre-
sponding to zero degrees phase error. The falling
edge of Fref, in conjunction with the ”up” signal,
causes the fine counter to then start counting up.
The coarse counter is inhibited by the fine counter
until the fine counter has reached it’s maximum
count. The falling edge of Fmtr causes the count-
ers to stop counting and the bits in the fine and
course counters are then latched into their re-
spective latches. The counters are then reset to
10000000 in anticipation of the next phase meas-
urement.
The operation of the counter section during spin-
up and phase lock can be described in three
phases:
1) Initial Spin-Up - At start-up the PLL will inher-
ently bring the motor speed ”in line” with the refer-
ence frequency.The phase detector is initialized
at power up to force the counters to start counting
up.
Since there will be many more Fref. vs Fmtr fall-
ing edges at start-up, the width of the ”up” pulse
will be wide. The fine counter will reach it’s maxi-
mum count and send an enable pulse to the
coarse counter causing it to start counting. After
127 counts, the coarse counter also reaches it’s
maximum count. At the end of the ”up” pulse, it’s
rising edge loads the outputs of the Coarse and
Fine counters into corresponding latches. Thus
the latches are updated once-per-rev with a bi-
nary number that corresponds to the measured
phase error. This count will be converted via a
Digital to Analog Convertors (DAC) into a speed
Command Voltage, which at start-up will be the
maximum as set by the ILIM SET voltage.
2) Overshoot - As the motor speed increases
close to the reference, the coarse counter comes
out of compliance and decreases it’s count as the
phase difference becomes smaller. The fine
counter then takes over when the phase is in a
certain range. A certain amount of phase over-
shoot will take place as the motor passes though
zero phase difference due to the closed loop sys-
tem response characteristics.
This will cause the counters to count down to
”slow” the motor down until the phase difference
is minimal.
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