LRS1338A View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1338A' PDF : 36 Pages View PDF
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
GENERAL DESIGN GUIDELINES
Supply Power
Maximum difference (between F-VCC and S-VCC) of
the voltage is less than 0.3 V.
Power Supply and Chip Enable of Flash
Memory and SRAM
It is forbidden that both F-CE and S-CE should be
LOW simultaneously. If the two memories are active
together, they many not operate normally due to inter-
ference noises or data collision on I/O bus. Both F-VCC
and S-VCC need to be applied by the recommended
supply voltage at the same time except SRAM data
retention mode.
SRAM Data Retention
SRAM data retention is capable in three ways.
SRAM power switching between a system battery and
a backup battery needs careful device decoupling from
Flash Memory to prevent SRAM supply voltage from
falling lower than 2.0 V by a Flash Memory peak cur-
rent caused by transition of Flash Memory supply volt-
age or of control signals (F-CE, F-OE, and RP).
CASE 1: FLASH MEMORY IS IN STANDBY MODE
(F-VCC = 2.7 V TO 3.6 V)
• SRAM inputs and input/outputs except S-CE need to
be applied with voltages in the range of -0.3 V to
S-VCC + 0.3 V or to be open (HIGH-Z).
• Flash Memory inputs and input/outputs except F-CE
and RP need to be applied with voltages in the range
of -0.3 V to S-VCC + 0.3 V or to be open (HIGH-Z).
CASE 2: FLASH MEMORY IS IN DEEP POWER
DOWN MODE (F-VCC = 2.7 V TO 3.6 V)
• SRAM inputs and input/outputs except S-CE need to
be applied with voltages in the range of -0.3 V to
S-VCC + 0.3 V or to be open.
• Flash Memory inputs and input/outputs except RP
need to be applied with voltages in the range of -0.3 V
to S-VCC + 0.3 V or to be open (HIGH-Z). RP needs to
be at the same level as F-VCC or to be open.
CASE 3: FLASH MEMORY POWER SUPPLY IS
TURNED OFF (F-VCC = 0 V)
• Fix RP LOW level before turning off Flash memory
power supply.
• SRAM inputs and input/outputs except S-CE need to
be applied with voltages in the range of -0.3 V to
S-VCC + 0.3 V or to be open (HIGH-Z).
• Flash Memory inputs and input/outputs except RP
need to be applied with voltages in the range of
-0.3 V to S-VCC + 0.3 V or to be open (HIGH-Z).
Power Up Sequence
When turning on Flash memory power supply, keep
RP LOW. After F-VCC reaches over 2.7 V, keep RP
LOW for more than 100 ns.
Device Decoupling
The power supply needs to be designed carefully
because one of the SRAM and the Flash Memory is in
standby mode when the other is active. A careful
decoupling of power supplies is necessary between
SRAM and Flash Memory. Note peak current caused
by transition of control signals (F-CE, S-CE).
Table 2. Truth Table1,2
F-CE
L
L
L
H
H
H
H
X
F-OE F-WE F-RP
L
H
H
H
H
H
H
L
H
X
X
X
X
X
X
X
X
X
X
X
H
X
X
L
S-CE S-OE S-WE ADDRESS
MODE
H
X
X
H
X
X
H
X
X
L
L
H
L
H
H
L
X
L
H
X
X
H
X
X
X
Flash read
X
Flash read
X
Flash write
X
SRAM read
X
SRAM read
X
SRAM write
X
Standby
X
Deep power down
I/O0 to
I/O15
Output
HIGH-Z
Input
Output
HIGH-Z
Input
HIGH-Z
HIGH-Z
CURRENT
ICC
ICC
ICC
ICC
ICC
ICC
ISB
ISB
NOTE
3, 4
5
4, 6, 7
5
NOTES:
1. F-CE should not be LOW when S-CE is LOW simultaneously.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH
for F-VPP. See DC Characteristics for VPPLK and VPPH voltages.
3. Refer to DC Characteristics. When F-VPP ≤ VPPLK, memory con-
tents can be read, but not altered.
4. Do not use in a timing that both F-OE and F-WE is LOW level.
5. F-RP at GND ± 0.2 V ensures the lowest deep power down current.
6. Command writes involving block erase, write, or lock-bit configura-
tion are reliably executed when F-VPP = VPPH and F-VCC = VCC1
block erase or word write operations with VIH < F-RP < VHH or
TA < -30°C produce spurious results and should not be attempted.
7. Refer to Table 6 for valid DIN during a write operation.
Data Sheet
3
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