LRS1338A View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1338A' PDF : 36 Pages View PDF
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
Principles of Operation
The LRS1388A SmartVoltage flash memory
includes an on-chip WSM to manage block erase and
word write functions. It allows for: 100% TTL-level con-
trol inputs, fixed power supplies during block erasure,
word write, and minimal processor overhead with
RAM-like interface timings.
After initial device power-up or return from deep
power-down mode (see ‘Bus Operation’), the device
defaults to read array mode. Manipulation of external
memory control pins allow array read, standby, and
output disable operations.
Status register and identifier codes can be accessed
through the CUI independent of the F-VPP voltage.
High voltage on F-VPP enables successful block era-
sure and word writing. All functions associated with
altering memory contents — block erase, word write,
status, and identifier codes — are accessed via the CUI
and verified through the status register.
Commands are written using standard microproces-
sor write timings. The CUI contents serve as input to
the WSM, which controls the block erase and word
write. The internal algorithms are regulated by the
WSM including pulse repetition, internal verification,
and margining of data. Addresses and data are inter-
nally latched during write cycles. Writing the appropri-
ate command outputs array data, accesses the
identifier codes or outputs status register data.
Interface software that initiates and polls progress of
block erase and word write can be stored in any block.
This code is copied to and executed from system RAM
during flash memory updates. After successful comple-
tion, reads are again possible via the Read Array com-
mand. Block erase suspend allows system software to
suspend a block erase to read/write data from/to blocks
other than that which is suspended. Word write sus-
pend allows system software to suspend a word write to
read data from any other flash memory array location.
DATA PROTECTION
Depending on the application, the system designer
may choose to make the VPP power supply switchable
(available only when memory block erases or word
writes are required) or hardwired to VPPH. The device
accommodates either design practice and encourages
optimization of the processor-memory interface.
When VPP ≤ VPPLK, memory contents cannot be
altered. The CUI, with two-step block erase or word
write command sequences, provides protection from
unwanted operations even when high voltage is
applied to VPP. All write functions are disabled when
VCC is below the write lockout voltage VLKO or when
RP is at VIL. The device’s boot blocks locking capabil-
ity for WP provides additional protection from inad-
vertent code or data alteration by block erase and
word write operations.
7FFFF
7F000
7EFFF
FE000
7DFFF
7D000
7CFFF
7C000
7BFFF
7B000
7AFFF
7A000
79FFF
79000
78FFF
78000
77FFF
70000
6FFFF
68000
67FFF
60000
5FFFF
58000
57FFF
50000
4FFFF
48000
47FFF
40000
3FFFF
38000
37FFF
30000
2FFFF
28000
27FFF
20000
1FFFF
18000
17FFF
10000
0FFFF
08000
07FFF
00000
TOP BOOT
4K-WORD BOOT BLOCK
0
4K-WORD BOOT BLOCK
1
4K-WORD PARAMETER BLOCK
0
4K-WORD PARAMETER BLOCK
1
4K-WORD PARAMETER BLOCK
2
4K-WORD PARAMETER BLOCK
3
4K-WORD PARAMETER BLOCK
4
4K-WORD PARAMETER BLOCK
5
32K-WORD MAIN BLOCK
0
32K-WORD MAIN BLOCK
1
32K-WORD MAIN BLOCK
2
32K-WORD MAIN BLOCK
3
32K-WORD MAIN BLOCK
4
32K-WORD MAIN BLOCK
5
32K-WORD MAIN BLOCK
6
32K-WORD MAIN BLOCK
7
32K-WORD MAIN BLOCK
8
32K-WORD MAIN BLOCK
9
32K-WORD MAIN BLOCK
10
32K-WORD MAIN BLOCK
11
32K-WORD MAIN BLOCK
12
32K-WORD MAIN BLOCK
13
32K-WORD MAIN BLOCK
14
Figure 4. Memory Map
LRS1338A-4
Data Sheet
9
Share Link: 
