LRS1338A View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1338A' PDF : 36 Pages View PDF
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
COMMAND DEFINITIONS
When VPP ≤ VPPLK, Read operations from the status
register, identifier codes or blocks are enabled. Placing
VPPH on VPP enables successful block erase and word
write operations.
Device operations are selected by writing specific com-
mands into the CUI. Table 6 defines these commands.
Table 5. Bus Operations
MODE
RP
CE
OE
WE ADDRESS VPP I/O0 - I/O15 NOTES
Read
VIH or VHH
VIL
VIL
VIH
X
X
DOUT
1, 2, 3
Output Disable
VIH or VHH
VIL
VIH
VIH
X
X
HIGH Z
Standby
VIH or VHH VIH
X
X
X
X
HIGH Z
Deep Power-Down
VIL
X
X
X
X
X
HIGH Z
4
Read Identifier Codes VIH or VHH VIL
VIL
VIH See Figure 3 X
5
Write
VIH or VHH
VIL
VIH
VIL
X
X
DIN
3, 6, 7
NOTES:
1. Refer to ‘DC Characteristics’. When VPP ≤ VPPLK, memory contents can be read, but not altered.
2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH for VPP.
See ‘DC Characteristics’ for VPPLK and VPPH voltages.
3. Never hold OE LOW and WE LOW at the same time.
4. RP at GND ± 0.2 V ensures the lowest deep power-down current.
5. See ‘Read Identifier Codes Command’ for read identifier code data.
6. Command writes involving block erase or word write are reliably executed when VPP = VPPH and VCC = VCC1.
Block erase or word write with VIH < RP < VHH produce spurious results and should not be attempted.
7. Refer to Table 6 for valid DIN during a write operations.
COMMAND
Read Array/Reset
Read Identifier Codes
Read Status Register
Clear Status Register
Block Erase
Word Write
Block Erase and Word
Write Suspend
Block Erase and Word
Write Resume
Table 6. Command Definitions1
BUS CYCLES
REQUIRED
1
≥2
2
1
2
2
FIRST BUS CYCLE
OPER.2 ADDR.3
DATA4
Write
X
FFH
Write
X
90H
Write
X
70H
Write
X
50H
Write
BA
20H
Write
WA 40H or 10H
SECOND BUS CYCLE
OPER.2 ADDR.3 DATA4
Read
IA
ID
Read
X
SRD
Write
BA
D0H
Write
WA
WD
NOTES
5
6
6, 7
1
Write
X
B0H
6
1
Write
X
D0H
6
NOTES:
1. Commands other than those shown in table are reserved by SHARP for
future device implementations and should not be used.
2. BUS operations are defined in Table 5.
3. X = Any valid address within the device; IA = Identifier Code Address, see Figure 5.
BA = Address within the block being erased; WA = Address of memory location to be written.
4. SRD = Data read from status register. See Table 9 for a description of the status register bits.
WD = Data to be written at location WA. Data is latched on the rising edge of WE or CE (whichever goes HIGH first).
ID = Data read from identifier codes.
5. Following the Read Identifier Codes command, read operations access manufacturer and device codes.
See ‘Read Identifier Codes Command’ for read identifier code data.
6. When WP = VIL, RP must beat VHH to enable block erase or word write operations.
Attempts to issue a block erase or word write to a locked boot block while RP = VIH.
7. Either 40H or 10H are recognized by the WSM as the word write setup.
Data Sheet
11
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