LRS1338A View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1338A' PDF : 36 Pages View PDF
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
WORD WRITE COMMAND
Word write is executed by a two-cycle command
sequence. Word write setup (standard 40H or alternate
10H) is written, followed by a second write that speci-
fies the address and data (latched on the rising edge of
WE). The WSM then takes over, controlling the word
write and write verify algorithms internally. After the
word write sequence is written, the device automati-
cally outputs status register data when read (see Fig-
ure 7). The CPU can detect the completion of the word
write event by analyzing the status register bit SR.7.
When word write is complete, status register bit
SR.4 should be checked. If word write error is detected,
the status register should be cleared. The internal
WSM verify only detects errors for ‘1’s that do not suc-
cessfully write to ‘0’s. The CUI remains in read status
register mode until it receives another command.
Reliable word writes can only occur when VCC = VCC1
and VPP and VPPH. In the absence of this high voltage,
memory contents are protected against word writes. If
word write is attempted while VPP ≤ VPPLK, status regis-
ter bits SR.3 and SR.4 will be set to ‘1’.
Successful word write for boot blocks requires that if
set, that WP = VIH or RP = VHH. If word write is
attempted to boot block when the corresponding WP =
VIL or RP = VIH, SR.1 and SR.4 will be set to ‘1’. Word
write operations with VIH < RP < VHH produce spurious
results and should not be attempted.
BLOCK ERASE SUSPEND COMMAND
The Block Erase Suspend command allows block-
erase interruption to read or word-write data in another
block of memory. Once the block-erase process starts,
writing the Block Erase Suspend command requests
that the WSM suspend the block erase sequence at a
predetermined point in the algorithm. The device out-
puts status register data when read after the Block
Erase Suspend command is written. Polling status reg-
ister bits SR.7 and SR.6 can determine when the block
erase operation has been suspended (both will be set
to ‘1’). Specification tWHRH2 defines the block erase
suspend latency.
At this point, a Read Array command can be written
to read data from blocks other than that which is sus-
pended. A Word Write command sequence can also be
issued during erase suspend to program data in other
blocks. using the Word Write Suspend command (see
‘Word Write Suspend Command’ section), a word write
operation can also be suspended. During a word write
operation with block erase suspended, status register
bit SR.7 will return to ‘0’. However, SR.6 will remain ‘1’
to indicate block erase suspend status.
The only other valid commands while block erase is
suspended are Read Status Register and Block Erase
Resume. After a Block Erase Resume command is
written to the flash memory, the WSM will continue the
block erase process. Status register bits SR.6 and
SR.7 will automatically clear. After the Erase Resume
command is written, the device automatically outputs
status register data when read (see Figure 8). VPP
must remain at VPPH (the same VPP level used for
block erase) while block erase is suspended. RP must
also remain at VIH or VHH (the same RP level used for
block erase). WP must also remain at VIL or VIH (the
same WP level used for block erase). Block erase can-
not resume until word write operations initiated during
block erase suspend have completed.
14
Data Sheet
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