LRS1338A View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1338A' PDF : 36 Pages View PDF
Stacked Chip (8M Flash & 2M SRAM)
LRS1338A
Design Considerations
THREE-LINE OUTPUT CONTROL
The device will often be used in large memory
arrays. SHARP provides three control inputs to accom-
modate multiple memory connections. Three-line con-
trol provides for:
• Lowest possible memory power dissipation.
• Complete assurance that data bus contention will
not occur.
To use these control inputs efficiently, an address
decoder should enable CE while OE should be con-
nected to all memory devices and the system’s READ
control line. This assures that only selected memory
devices have active outputs while deselected memory
devices are in standby mode. RP should be connected
to the system POWERGOOD signal to prevent unin-
tended writes during system power transitions. POW-
ERGOOD should also toggle during system reset.
POWER SUPPLY DECOUPLING
Flash memory power switching characteristics
require careful device decoupling. System designers
are interested in three supply current issues: standby
current levels, active current levels and transient peaks
produced by falling and rising edges of CE and OE.
Transient current magnitudes depend on the device
outputs’ capacitive and inductive loading. Two-line
control and proper decoupling capacitor selection will
suppress transient voltage peaks. Each device should
have a 0.1 µF ceramic capacitor connected between its
VCC and GND and between its VPP and GND. These
high-frequency, low inductance capacitors should be
placed as close as possible to package leads. Addition-
ally, for every eight devices, a 4.7 µF electrolytic capac-
itor should be placed at the array’s power supply
connection between VCC and GND. The bulk capacitor
will overcome voltage slumps caused by PC board
trace inductance.
VPP TRACE ON PRINTED CIRCUIT BOARDS
Updating flash memories that reside in the target
system requires that the printed circuit board designer
pay attention to the VPP power supply trace. The VPP
pin supplies the memory cell current for word writing
and block erasing. Use similar trace widths and layout
considerations given to the VCC power bus. Adequate
VPP supply traces and decoupling will decrease VPP
voltage spikes and overshoots.
VCC, VPP RP TRANSITIONS
Block erase and word write are not guaranteed if
VPP falls outside of a valid VPPH range, VCC falls out-
side of a valid VCC1 range, or RP ≠ VIH or VHH. If VPP
error is detected, status register bit SR.3 is set to ‘1’
along with SR.4 or SR.5, depending on the attempted
operation. If RP transitions to VIL during block erase or
word write, the operation will abort and the device will
enter deep power-down. The aborted operation may
leave data partially altered. Therefore, the command
sequence must be repeated after normal operation is
restored. Device power-off or RP transitions to VIL clear
the status register.
The CIU latches commands issued by system soft-
ware and is not altered by VPP or CE transitions or
WSM actions. Its state is read array mode upon power-
up, after exit from deep power-down or after VCC tran-
sitions below VLKO.
After block erase or word write, even after VPP tar-
nation down to VPPLK, the CUI must be placed in read
array mode via the Read Array command if subsequent
access to the memory array is desired.
POWER-UP/DOWN PROTECTION
The device is designed to offer protection against
accidental block erasure or word writing during power
transitions. Upon power-up, the device is indifferent as
to which power supply (VPP or VCC) powers-up first.
Internal circuitry resets the CUI to read array mode at
power-up.
A system designer must guard against spurious
writes for VCC voltages above VLKO when VPP is active.
Since both WE and CE must be LOW for a command
write, driving either to VHH will inhibit writes. The CUI’s
two-step command sequence architecture provides
added level of protection against data alteration.
WP provide additional protection from inadvertent
code or data alteration.
The device is disabled while RP = VIL regardless of
its control inputs state.
POWER DISSIPATION
When designing portable systems, designers must
consider battery power consumption not only during
device operation, but also for data retention during sys-
tem idle time. Flash memory’s non-volatility increases
usable battery life because data is retained when sys-
tem power is removed.
In addition, deep power-down mode ensures
extremely low power consumption even when system
power is applied. For example, portable computing
products and other power sensitive applications that
use an array of devices for solid-state storage can con-
sume negligible power by lowering RP to VIL standby or
sleep modes. If access is again needed, the devices
can be read following the tPHQV and tPHWL wake-up
cycles required after RP is first raised to VIH. See ‘AC
Characteristics — Read Only and Write Operations’
and Figure 12, 13 and 14 for more information.
Data Sheet
19
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