LRS1338A View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1338A' PDF : 36 Pages View PDF
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
SYMBOL
A0 - A18
I/O0 - I/O15
CE
RP
OE
WE
WP
VPP
VCC
GND
Table 4. Flash Pin Descriptions
TYPE
NAME AND FUNCTION
Input
ADDRESS INPUTS: Inputs for addresses during read and write operations.
Addresses are internally latched during the write cycle.
Input/Output
DATA INPUT/OUTPUTS: Inputs data and commands during CUI write cycles; out-
puts data during memory array, status register, and identifier code read cycles. Data
pins float to HIGH-impedance when the chip is deselected or outputs are disabled.
Data is internally latched during a write cycle.
Input
CHIP ENABLE: Activates the device’s control logic, input buffers, decoders, and
sense amplifiers. CE-HIGH deselects the device and reduces power consumption
to standby levels.
Input
RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and
resets internal automation. RP-HIGH enables normal operation. When driven
LOW, RP inhibits write operations which provides data protection during power
transitions. Exit from deep power-down sets the device to read array mode. With
RP = VHH, block erase or word write can operate to all blocks without WP state.
Block erase or word write with VIH < RP < VHH produce spurious results and should
not be attempted.
Input
OUTPUT ENABLE: Gates the device’s outputs during a read cycle.
Input
WRITE ENABLE: Controls writes to the CIU and array blocks. Addresses and data
are latched on the rising edge of the WE pulse.
Input
WRITE PROTECT: Master control for boot blocks locking. When VIL, locked boot
blocks cannot be erased and programmed.
Supply
Supply
BLOCK ERASE and WORD WRITE POWER SUPPLY: For erasing array blocks or
writing words. With VPP ≤ VPPLK, memory contents cannot be altered. Block erase
and word write with an invalid VPP (see ‘DC Characteristics’) produce spurious
results and should not be attempted.
DEVICE POWER SUPPLY: Do not float any power pins. With VCC ≤ VLKO, all
write attempts to the flash memory are inhibited. Device operations at invalid
VCC voltage (see ‘DC Characteristics’) produce spurious results and should not
be attempted.
Supply GROUND: Do not float any ground pins.
8
Data Sheet
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