LRS1338A View Datasheet(PDF) - Sharp Electronics
Part Name
Description
MFG CO.
'LRS1338A' PDF : 36 Pages View PDF
LRS1338A
Stacked Chip (8M Flash & 2M SRAM)
FLASH MEMORY*
New Features
The LRS1388A flash memory maintains backwards
compatibility with SHARP’s LH28F800BG-L.
• SmartVoltage technology
• Enhanced suspend capabilities
• Boot block architecture
Please note the following important differences:
• VPPLK has been lowered to 1.5 V to support 3.0 V
block erase and word write operations. Designs that
switch VPP off during read operations should make
sure that the VPP voltage transitions to GND.
• Allow VPP connection to 3.0 V.
Product Overview
The LRS1338A is a high-performance 8M Smart-
Voltage flash memory organized as 512K-word of 16
bits. The 512K-word of data is arranged in two 4K-word
boot blocks, six 4K-word parameter blocks and fifteen
32K-word main blocks which are individually erasable
in-system. The memory map is shown in Figure 4.
SmartVoltage technology provides a choice of VCC
and VPP combinations, as shown in Table 3, to meet
system performance and power expectations. In addi-
tion to flexible erase and program voltages, the dedi-
cated VPP pin gives complete data protection when
VPP ≤ VPPLK.
Table 3. VCC and VPP Voltage Combinations
VCC Voltage
2.7 V to 3.6 V
VPP Voltage
2.7 V to 3.6 V
Internal VCC and VPP detection circuitry automati-
cally configures the device for optimized read and write
operations.
A Command User Interface (CUI) serves as the
interface between the system processor and internal
operation of the device. A valid command sequence
written to the CUI initiates device automation. An inter-
nal Write State Machine (WSM) automatically executes
the algorithms and timings necessary for block erase
and word write operations.
A block erase operation erases on e of the device’s
32K-word blocks typically within 1.14 seconds, 4K-
word blocks typically within 0.38 seconds independent
of other blocks. Each block can be independently
erased 100,000 times. Block erase suspend mode
allows system software to suspend block erase to read
or write data from any other block.
Writing memory data is performed in word increments
of the device’s 32K-word blocks typically within 44.6 µs,
4K-word blocks typically within 45.9 µs. Word write sus-
pend mode enables the system to read data or execute
code from any other flash memory array location.
The boot blocks can be locked for the WP pin. Block
erase or word write for boot block must not be carried
out by WP to LOW and RP to VIH.
The status register indicates when the WSM’s block
erase or word write operation is finished.
The access time is 120 ns (tAVQV) over the commer-
cial temperature range (-40°C to +85°C) and VCC sup-
ply voltage range of 2.7 V to 3.6 V.
The Automatic Power Savings (APS) feature sub-
stantially reduces active current when the device is in
static mode (addresses not switching). In APS mode,
the typical ICCR current is 1 mA at 3.3 V VCC.
When CE and RP pins are at VCC, the ICC CMOS
standby mode is enabled. When the RP pin is at GND,
deep power-down mode is enabled which minimizes
power consumption and provides write protection dur-
ing reset. A reset time (tPHQV) is required from RP
switching HIGH until outputs are valid. Likewise, the
device has a wake time (tPHEL) from RP HIGH until
writes to the CUI are recognized. With RP at GND, the
WSM is reset and the status register is cleared.
NOTE: *In the Flash Memory section all reference to pins, com-
mands, voltage, etc. refer only to the Flash portion of this chip.
6
Data Sheet
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