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LRS1383 View Datasheet(PDF) - Sharp Electronics

Part Name
Description
MFG CO.
LRS1383
Sharp
Sharp Electronics Sharp
'LRS1383' PDF : 114 Pages View PDF
FUM00701
57
5 Design Considerations
5.1 Hardware Design Considerations
5.1.1 Control using RST#, CE# and OE#
The device will often be used in large memory arrays.
SHARP provides three control input pins to
accommodate multiple memory connection. Three
control input pins, RST#, CE# and OE# provide for:
Minimize the power consumption of the memory
Avoid data confliction on the data bus
To effectively use these control input pins, access the
desired memory by enabling the CE# through the address
decoder. Connect OE# to READ# control signal of all
memory devices and system. With these connections, the
selected memory devices are activated and deselected
memory devices are in standby mode. RST# should be
connected to the system POWERGOOD signal to prevent
unintended writes during system power transitions.
POWERGOOD should toggle (once set to VIL) during
system reset.
5.1.2 Power Supply Decoupling
Flash memorys power switching characteristics require
careful device decoupling for eliminating noises to the
system power lines. System designers should consider
standby current levels (ICCS), active current levels (ICCR)
and transient peaks produced by falling and rising edges
of CE# and OE#. Transient current magnitudes depend on
the device outputscapacitive and inductive loading.
Two-line control and proper decoupling capacitor
selection will suppress these transient voltage peaks. Each
flash device should have a 0.1 F ceramic capacitor
connected between each VCC, VCCQ and GND and
between VPP and GND (when VPP is used as 12V
supply). These high-frequency, inherently low-inductance
capacitors should be placed as close as possible to the
package leads. Additionally, for every eight devices, a
4.7 F electrolytic capacitor should be placed at the
arrays power supply connection between VCC and GND.
These capacitors will overcome voltage slumps caused by
circuit board trace inductance.
5.1.3 VPP Traces on Printed Circuit Boards
The VPP pin on the LH28F320BX/LH28F640BX series
Flash memory is only used to monitor the power supply
voltage and is not used for a power supply pin except for
12V supply. Therefore, even when on-board writing to
the flash memory on the system, it is not required to
consider that VPP supplies the currents on the printed
circuit boards.
However, in erase or program operations with applying
12V±0.3V to VPP pin, VPP is used for the power supply
pin. When executing these operations, VPP trace widths
and layout should be similar to that of VCC to supply the
flash memory cells current for erasing or programming.
Adequate VPP supply traces, and decoupling capacitors
placed adjacent to the component, will decrease spikes
and overshoots.
5.1.4 VCC, VPP, RST# Transitions
If VPP is lower than VPPLK, VCC is lower than VLKO, or
RST# is not at VIH, block erase, full chip erase, (page
buffer) program and OTP program operation are not
guaranteed. When VPP error is detected, the status
register bits SR.5 or SR.4 (depending on the attempted
operation) and SR.3 will be set to "1". If RST# transitions
to VIL during the block erase, full chip erase, (page
buffer) program or OTP program operation, the status
register bit SR.7 will remain "0" until reset operation has
been completed. Then, the attempted operation will be
aborted and the device will enter reset mode after the
completion of the reset sequence. If RST# is taken VIL
during a block erase, full chip erase, (page buffer)
program or OTP program operation, the memory contents
at the aborted location are no longer valid. Therefore, the
proper command must be written again. And also, if VCC
transitions to lower than VLKO during a block erase, full
chip erase, (page buffer) program or OTP program
operation, the attempted operation will be aborted and the
memory contents at the aborted location are no longer
valid. Write the proper command again after VCC
transitions above VLKO.
Appendix to Spec No.: MFM2-J13207 Model No.: LRS1383 March 1, 2001
Rev. 2.20
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